Ports and Attributes
Table5-4 defines the shared clocking ports.Table 5-4:
PortCLKIN
Shared Clocking Ports
DirIn
Clock Domain
N/A
Description
Reference clock input to the shared PMA PLL.The REFCLKOUT port from each GTX_DUAL tile provides access to the reference clock provided to the shared PMA PLL (CLKIN). It can be routed for use in the FPGA logic.
REFCLKOUTOutN/A
Table5-5 defines the shared clocking attributes.Table 5-5:
Shared Clocking Attributes
Type
Description
CLK25_DIVIDER is set to get an internal clock for the tile.1: CLKIN < 25 MHz2: 25MHz < CLKIN < 50 MHz3: 50MHz < CLKIN < 75 MHz4: 75MHz < CLKIN < 100 MHz5: 100MHz < CLKIN < 125 MHz6: 125MHz < CLKIN < 150 MHz10: 150MHz < CLKIN < 250 MHz12: CLKIN > 250MHz
Must be set to TRUE. Oscillators driving the dedicated reference clock inputs must be AC coupled.
CLKINDC_B
Boolean
When set to FALSE for testing, the common mode voltage of the driving circuit must match the common mode voltage of the differential clock input pair (MGTCLKP, MGTCLKN). The differential swing must not exceed the maximum differential swing of the clock input pair.(1, 2)When set to FALSE, switches off the internal termination resistors of the differential clock input pair. This results in a high impedance input characteristic that is only intended for testing.
CLKRCV_TRST
Boolean
When set to TRUE, the differential clock input is nominally terminated with a 100Ω differential impedance. Each clock input in (MGTCLKP,
MGTCKLKN) is contacted via a 50Ω resistor to a midterm nominal voltage of 0.8V.(1, 2)
Attribute
CLK25_DIVIDERInteger
Notes:
1.Violation of the rules outlined in this section result in a marginal or dysfunctional design, devicedegradation in the future, or device damage.
2.Consult DS202: Virtex-5 FPGA Data Sheet for the common mode voltage values and the associateddifferential swing and operating conditions.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Reset
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 5:Tile Features
X-Ref Target - Figure 5-7GTX_DUAL RESET After ConfigurationGTX0RXCDRRESET0RXRESET0TXRESET0TXRESET1GTX1RXCDRRESET1RXRESET1RXBUFRESET0RXBUFRESET1UG198_c5_07_052107Figure 5-7:GTX_DUAL Reset Hierarchy
Ports and Attributes
Table5-6 defines the shared tile reset ports.
Table 5-6:
Shared Tile Reset PortsPort
Dir
Domain
Description
This port is driven High and then deasserted to start the full GTX_DUAL reset sequence. This sequence takes about 120μs to complete, and systematically resets all subcomponents of the GTX_DUAL tile.
This port goes High when the GTX transceiver has finished reset and is ready for use. For this signal to work correctly, CLKIN and all clock inputs on the individual GTX transceiver (TXUSRCLK, TXUSRCLK2, RXUSRCLK, RXUSRCLK2) must be driven.This active-High signal resets the RX elastic buffer logic.
GTXRESET(1)(2)
InAsync
RESETDONE0 RESETDONE1RXBUFRESET0(1)RXBUFRESET1(2)RXCDRRESET0(1)RXCDRRESET1(2)RXRESET0(1)RXRESET1(2)TXRESET0(1)TXRESET1(2)
Notes:
OutAsync
InAsync
In
Individual reset signal for the RX CDR and the RX part of the PCS
RXUSRCLK2for this channel. This signal is driven High to cause the CDR to give
up its current lock and return to the shared PMA PLL frequency.
AsyncAsync
Active-High reset for the RX PCS logic.
Resets the PCS of the GTX transmitter, including the phase adjust FIFO, the 8B/10B encoder, and the FPGA TX interface.
InIn
1.When these resets are active, then RESETDONE0 is driven Low. All resets are asynchronous, positive-edge triggered, andsynchronized internally to a specific clock domain.
2.When these resets are active, then RESETDONE1 is driven Low. All resets are asynchronous, positive-edge triggered, andsynchronized internally to a specific clock domain.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
TX Out-of-Band/Beacon Signaling
TX Out-of-Band/Beacon Signaling
Overview
Each GTX transceiver provides support for generating the Out-of-Band (OOB) sequences described in the Serial ATA (SATA) specification and beaconing described in the PCI
Express specification. See AppendixB, “OOB/Beacon Signaling,” for an overview of OOB signaling and how it is used in these protocols.
GTX_DUAL support for SATA OOB signaling consists of the analog circuitry required to encode the OOB signal state and state machines to format bursts of OOB signals for SATA COM sequences (COMRESET, COMWAKE, and COMINIT). Each GTX transceiver also supports SATA auto-negotiation by allowing the timing of the COM sequences to be changed based on the divider settings used for the TX line rate.
GTX_DUAL supports beaconing as described in the PHY Interface for the PCI Express (PIPE) Specification. The format of the beacon sequence is controlled by the FPGA logic.
Ports and Attributes
Table6-20 describes the ports that control OOB/beacon signaling.
Table 6-20:
TX OOB/Beacon Signaling Ports
Direction
Domain
Description
The decoding of RXSTATUS[2:0] depends on the setting of RX_STATUS_FMT:
?When RX_STATUS_FMT = PCIE:
RXSTATUS0[2:0]RXSTATUS1[2:0]
Out
RXUSRCLK2
RXSTATUS is not used for PCIe TXELECIDLE?When RX_STATUS_FMT = SATA:
RXSTATUS[0]: TXCOMSTART operation completeRXSTATUS[1]: COMWAKE signal received
RXSTATUS[2]: COMRESET/COMINIT signal received
TXCOMSTART0TXCOMSTART1TXCOMTYPE0TXCOMTYPE1TXELECIDLE0TXELECIDLE1
TXPOWERDOWN0[1:0]TXPOWERDOWN1[1:0]
In
TXUSRCLK2
Initiates the transmission of the COM* sequence selected by TXCOMTYPE (SATA only).
Selects the type of COM signal to send (SATA only):
In
TXUSRCLK2
0: COMRESET/COMINIT1: COMWAKE
In
TXUSRCLK2
When in the P2 power state, this signal controls whether an
electrical idle or a beacon indication is driven out onto the TX pair.Powers down the TX lanes. When in PCIe mode, the GTX_DUAL tile must be in the P2 power state (TXPOWERDOWN = 11) to generate beacon signaling. Use TXPOWERDOWN = 00 for SATA OOB signaling.
Port
InTXUSRCLK2
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
Table6-21 defines the OOB/beacon signaling attributes.Table 6-21:
TX OOB/Beacon Signaling Attributes
Type4-bit Binary
Description
Number of bursts in a COM sequence.
Tie to FALSE. When FALSE, PLL_SATA allows TX SATA operations to work at the SATA Generation 1 (1.5Gb/s) or SATA Generation 2 (3Gb/s) rate.Sets the divider for the TX line rate for the
individual GTX transceiver. Can be set to 1, 2, or 4.
Attribute
COM_BURST_VAL_0COM_BURST_VAL_1PLL_SATA_0PLL_SATA_1
PLL_TXDIVSEL_OUT_0PLL_TXDIVSEL_OUT_1
Boolean
Integer
Description
The GTX_DUAL tile supports two signaling modes: one for SATA operations and one for PCI Express operations. The use of these two mechanisms is mutually exclusive.
Beacon Signaling for PCI Express Operations
Beacon signaling for PCI Express operations is performed when the GTX_DUAL tile is in the P2 power state. Transmission of a beacon is initiated by the deassertion of
TXELECIDLE, as shown in Figure6-26. FPGA control logic controls beacon timing by the sequencing of TXELECIDLE.
X-Ref Target - Figure 6-26TXPOWERDOWN[1:0]11TXELECIDLETXN/TXPValid Beacon SignalingUG198_c6_26_101207Figure 6-26:Beacon Generation for PCI Express Operations
OOB Signaling for SATA Operations
OOB signaling for SATA operation is initiated through the use of the TXELECIDLE, TXCOMSTART, and TXCOMTYPE ports. When TXELECIDLE is held High, assertion of TXCOMSTART for one TXUSRCLK2 cycle initiates the transmission of a COM sequence. The type of COM sequence generated is controlled by the TXCOMTYPE port as shown in Table6-20.
The number of bursts in the COM sequence is controlled by the COM_BURST_VAL
attribute. The timing of the COM sequences transmitted is correct as long as the PLL clock (see “Shared PMA PLL,” page 86) is set to 1.5GHz, and PLL_TXDIVSEL_OUT for each channel is set to either 1 (for a 3.0 Gb/s SATA Generation2 rate) or 2 (for a 1.5 Gb/s SATA Generation1 rate).
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XQ17V16CK44M中文规格书 - 图文
