MEMORY存储芯片PC28F00AP30BFA中文规格书 - 图文

Two-Plane Read Operations

Two-plane read page operations improve data throughput by copying data from morethan one plane simultaneously to the specified cache registers. This is done by pre-pending one or more READ PAGE TWO-PLANE (00h-00h-30h) commands in front ofthe READ PAGE (00h-30h) command.

When the die (LUN) is ready, the RANDOM DATA READ TWO-PLANE (06h-E0h) com-mand determines which plane outputs data. During data output, the following com-mands can be used to read and modify the data in the cache registers: RANDOM DATAREAD (05h-E0h) and RANDOM DATA INPUT (85h).Two-Plane Read Cache Operations

Two-plane read cache operations can be used to output data from more than one cacheregister while concurrently copying one or more pages from the NAND Flash array tothe data register. This is done by prepending READ PAGE TWO-PLANE (00h-00h-30h)commands in front of the PAGE READ CACHE RANDOM (00h-31h) command.

To begin a two-plane read page cache sequence, begin by issuing a READ PAGE TWO-PLANE operation using the READ PAGE TWO-PLANE (00h-00h-30h) and READ PAGE(00h-30h) commands. R/B# goes LOW during tR and the selected die (LUN) is busy

(RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of thesecommands:

?READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential pages from thepreviously addressed planes from the NAND Flash array to the data registers.?READ PAGE TWO-PLANE (00h-00h-30h) [in some cases, followed by READ PAGE

CACHE RANDOM (00h-31h)] – copies the pages specified from the NAND Flash arrayto the corresponding data registers.

After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B#goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY whilethe next pages begin copying data from the array to the data registers. After tRCBSY,R/B# goes HIGH and the LUN’s status register bits indicate the device is busy with acache operation (RDY = 1, ARDY = 0). The cache registers become available and the pa-ges requested in the READ PAGE CACHE operation are transferred to the data registers.Issue the RANDOM DATA READ TWO-PLANE (06h-E0h) command to determine whichcache register will output data. After data is output, the RANDOM DATA READ TWO-PLANE (06h-E0h) command can be used to output data from other cache registers. Af-ter a cache register has been selected, the RANDOM DATA READ (05h-E0h) commandcan be used to change the column address of the data output.

After outputting data from the cache registers, either an additional TWO-PLANE READCACHE series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST(3Fh) command can be issued.

If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data registers are cop-ied into the cache registers. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1,indicating that the cache registers are available and that the die (LUN) is ready. Issue theRANDOM DATA READ TWO-PLANE (06h-E0h) command to determine which cacheregister will output data. After data is output, the RANDOM DATA READ TWO-PLANE(06h-E0h) command can be used to output data from other cache registers. After acache register has been selected, the RANDOM DATA READ (05h-E0h) command canbe used to change the column address of the data output.

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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Program Operations

Figure 45: PROGRAM PAGE CACHE (80h–15h) Operation (Start)

Cycle typeCommandAddressAddressAddressAddressAddresstADLDINDINDINDINCommandI/O[7:0]

80hC1C2R1R2R3D0D1…Dn15htWBtCBSYRDY

1Cycle typeI/O[7:0]CommandAddressAddressAddressAddressAddresstADL80hC1C2R1R2R3D0D1…Dn15htWBtCBSYDINDINDINDINCommandRDY1Figure 46: PROGRAM PAGE CACHE (80h–15h) Operation (End)

As defined forPAGE CACHE PROGRAMCycle typeCommandAddressAddressAddressAddressAddresstADLDINDINDINDINCommandI/O[7:0]80hC1C2R1R2R3D0D1…Dn15htWBtCBSYRDY1Cycle typeCommandAddressAddressAddressAddressAddresstADLDINDINDINDINCommandI/O[7:0]80hC1C2R1R2R3D0D1…Dn10htWBtLPROGRDY1PDF: 09005aef83b25735

m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Program Operations

PROGRAM PAGE TWO-PLANE (80h-11h)

The PROGRAM PAGE TWO-PLANE (80h-11h) command enables the host to input datato the addressed plane's cache register and queue the cache register to ultimately bemoved to the NAND Flash array. This command can be issued one or more times. Eachtime a new plane address is specified that plane is also queued for data transfer. To in-put data for the final plane and to begin the program operation for all previously

queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAMPAGE CACHE (80h-15h) command. All of the queued planes will move the data to theNAND Flash array. This command is accepted by the die (LUN) when it is ready(RDY = 1).

To input a page to the cache register and queue it to be moved to the NAND Flash arrayat the block and page address specified, write 80h to the command register. Unless thiscommand has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command,issuing the 80h to the command register clears all of the cache registers' contents on theselected target. Write five address cycles containing the column address and row ad-dress; data input cycles follow. Serial data is input beginning at the column address

specified. At any time during the data input cycle, the RANDOM DATA INPUT (85h) andPROGRAM FOR INTERNAL DATA INPUT (85h) commands can be issued. When datainput is complete, write 11h to the command register. The selected die (LUN) will gobusy (RDY = 0, ARDY = 0) for tDBSY.

To determine the progress of tDBSY, the host can monitor the target's R/B# signal or,alternatively, the status operations (70h, 78h) can be used. When the LUN's statusshows that it is ready (RDY = 1), additional PROGRAM PAGE TWO-PLANE (80h-11h)commands can be issued to queue additional planes for data transfer. Alternatively, thePROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be is-sued.

When the PROGRAM PAGE (80h-10h) command is used as the final command of a two-plane program operation, data is transferred from the cache registers to the NANDFlash array for all of the addressed planes during tPROG. When the die (LUN) is ready(RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of theplanes to verify that programming completed successfully.

When the PROGRAM PAGE CACHE (80h-15h) command is used as the final commandof a program cache two-plane operation, data is transferred from the cache registers tothe data registers after the previous array operations finish. The data is then movedfrom the data registers to the NAND Flash array for all of the addressed planes. This oc-curs during tCBSY. After tCBSY, the host should check the status of the FAILC bit for

each of the planes from the previous program cache operation, if any, to verify that pro-gramming completed successfully.

For the PROGRAM PAGE TWO-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and PRO-GRAM PAGE CACHE (80h-15h) commands, see Two-Plane Operations for two-plane ad-dressing requirements.

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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Program Operations

Figure 47: PROGRAM PAGE TWO-PLANE (80h–11h) Operation

Cycle typeCommandAddressAddressAddressAddressAddresstADLDINDINDINCommandCommandAddressI/O[7:0]80hC1C2R1R2R3D0…Dn11htWBtDBSY80h...RDY

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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Erase Operations

Erase Operations

Erase operations are used to clear the contents of a block in the NAND Flash array toprepare its pages for program operations.Erase Operations

The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK

TWO-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When thedie (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify thatthis operation completed successfully.TWO-PLANE ERASE Operations

The ERASE BLOCK TWO-PLANE (60h-D1h) command can be used to further systemperformance of erase operations by allowing more than one block to be erased in theNAND array. This is done by prepending one or more ERASE BLOCK TWO-PLANE (60h-D1h) commands in front of the ERASE BLOCK (60h-D0h) command. See Two-PlaneOperations for details.

ERASE BLOCK (60h-D0h)

The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flasharray. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).To erase a block, write 60h to the command register. Then write three address cyclescontaining the row address; the page address is ignored. Conclude by writing D0h to thecommand register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERSwhile the block is erased.

To determine the progress of an ERASE operation, the host can monitor the target's R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die(LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit.In devices that have more than one die (LUN) per target, during and following inter-leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) commandmust be used to select only one die (LUN) for status output. Use of the READ STATUS(70h) command could cause more than one die (LUN) to respond, resulting in bus con-tention.

The ERASE BLOCK (60h-D0h) command is used as the final command of an erase two-plane operation. It is preceded by one or more ERASE BLOCK TWO-PLANE (60h-D1h)commands. All blocks in the addressed planes are erased. The host should check thestatus of the operation by using the status operations (70h, 78h). See Two-Plane Opera-tions for two-plane addressing requirements.

Figure 48: ERASE BLOCK (60h-D0h) Operation

Cycle type

CommandAddressAddressAddressCommandI/O[7:0]RDY

60hR1R2R3D0htWBtBERSPDF: 09005aef83b25735

m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN