AppendixA
MGT to GTX Transceiver Design Migration
Overview
This appendix describes important differences regarding migration from the
Virtex?-IIPro and Virtex-4 multi-gigabit transceivers (MGTs) to the Virtex-5 FPGA RocketIO? GTX transceivers. This appendix does not describe all of the features and capabilities of these devices but only highlights relevant PCB, power supply, and reference clock differences. For more information on Virtex-II Pro and Virtex-4 FPGAs, refer to
Virtex-IIPro and Virtex-II Pro X Complete Data Sheet [Ref11], RocketIO Transceiver User Guide [Ref12], and Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide [Ref13].
Primary Differences
Virtex-5 FXT/TXT FPGAs are a different family from the Virtex-II Pro and Virtex-4 families. The Virtex-5 FXT/TXT devices are not pin compatible with these previous generation devices. However, many aspects of the MGTs and GTX transceivers are the same between families. The primary differences are:???????
Number of MGTs and GTX transceivers per deviceClocking
Serial rates and ranges
Encoding standards – 8B/10B, 64B/66B, SONET, and othersClock multiplier settings and PLL ranges
Flexibility due to partial reconfiguration, PMA programming bus, dynamicreconfiguration port (DRP)Board design guidelines
MGTs per Device
Virtex-5 FPGAs allow for a large range of GTP and GTX transceivers per device. TableA-1 shows the number of transceivers available for each family.Table A-1:
Transceivers per DeviceVirtex Device
Virtex-II Pro FPGAVirtex-4 FPGA
4, 8, 12, 16, 208, 12, 16, 20, 24
# of Transceivers
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Appendix A:MGT to GTX Transceiver Design Migration
RXSTATUS Bus
Several buses have changed over the FPGA generations to improve the information that is indicated. TableA-13 shows the migration from Virtex-II Pro to Virtex-5 devices.
Table A-13:
Status Bus Changes
Virtex-II Pro
MGTCHBONDONE(3)
N/A
Virtex-4 MGTRXSTATUS[5]RXSTATUS[4:3]
Virtex-5 FPGA(LXT and SXT) GTP Transceiver(1)RXCHANISALIGNED0RXCHANISALIGNED1
RXSTATUS[2:0]
Virtex-5 FPGA(FXT and TXT)GTX Transceiver(2)RXCHANISALIGNED0RXCHANISALIGNED1
RXSTATUS[2:0]
DescriptionIndicates channel bonding completeIndicates status bus is status, data, eventIndicates channel bonding or clock correction pointers change
Indicates that an RX buffer has
underflow/overflow
Notes:
RXCLKCORCNT0[2:0]RXCLKCORCNT0[2:0]
RXSTATUS[2:0]
RXCHANREALIGN0RXCHANREALIGN1RXCHANREALIGN0RXCHANREALIGN1
RXBUFSTATUS[1]RXBUFERRRXBUFSTATUS[2:0]RXBUFSTATUS[2:0]
1.Signal optimization settings are independent between both GTP transceivers of a GTP_DUAL tile. GTP0 is indicated by the suffix“0” after the signal name, and GTP1 is indicated by the suffix “1” (for example, RXEQMIX0 or RXEQMIX1).
2.Signal optimization settings are independent between both GTX transceivers of a GTX_DUAL tile. GTX0 is indicated by the suffix“0” after the signal name, and GTX1 is indicated by the suffix “1” (for example, RXEQMIX0 or RXEQMIX1).3.RXCLKCORCNT must go to 3'b101 before channel bonding is complete.
Pre-emphasis, Differential Swing, and Equalization
The differential signaling techniques are more robust in recent Xilinx transceivers. The Virtex-5 FPGA GTP and GTX transceivers add ports to control TX characteristics to
simplify reconfiguration. TableA-14 shows the migration of attributes from Virtex-II Pro and Virtex-4 MGTs to Virtex-5 FPGA GTP and GTX transceivers.
Table A-14:
Description
Signal Optimization Attributes and Ports
Virtex-II Pro
MGT
Virtex-5 FPGA
Virtex-4 MGT
GTP Transceivers(1)Ports
Attributes
Virtex-5 FPGA
GTX Transceivers(1)Ports
Attributes
Controls TXpre-emphasis and edge rate
TXPRE_PRDRV_DACTXPRE_TAP_PDTXSLEWRATE
TXPREEMPHASIS[3:0]TX_PREMPHASIS
TXPOST_PRDRV_DACTXDAT_PRDRV_DACTXPOST_TAP_PD
TXPRE_TAP_DACTXPOST_TAP_DACTXDAT_TAP_DAC
TXBUFDIFFCTRL0[2:0] TX_DIFF_TXBUFDIFFCTRL1[2:0] BOOST_0TXDIFFCTRL0[2:0] TX_DIFF_TXDIFFCTRL1[2:0]BOOST_1
TXPREEMPHASIS[3:0]
Controls
differential amplitude ofthe transmitted signal
TX_DIFF_CTRL
TXBUFDIFFCTRL0[2:0]TXBUFDIFFCTRL1[2:0] TXDIFFCTRL0[2:0] TXDIFFCTRL1[2:0]
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Appendix A:MGT to GTX Transceiver Design Migration
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Appendix C:8B/10B Valid Characters
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
UG198 (v3.0) October 30, 2009RocketIO GTX Transceiver User GuideTable D-2:
DRP Address by Attribute (Cont’d)
Attribute
Bit012345678910111213141516171819202122232425262728293031CLK_COR_SEQ_1_4_11a<5>1a<4>1a<3>1a<2>1a<1>1a<0>19<15>19<14>19<13>19<12>CLK_COR_SEQ_1_ENABLE_035<6>35<7>35<8>35<9>CLK_COR_SEQ_1_ENABLE_1
1a<9>1a<8>1a<7>1a<6>CLK_COR_SEQ_2_1_034<12>34<13>34<14>34<15>35<0>35<1>35<2>35<3>35<4>35<5>CLK_COR_SEQ_2_1_11b<3>1b<2>1b<1>1b<0>1a<15>1a<14>1a<13>1a<12>1a<11>1a<10>CLK_COR_SEQ_2_2_034<2>34<3>34<4>34<5>34<6>34<7>34<8>34<9>34<10>34<11>CLK_COR_SEQ_2_2_11b<13>1b<12>1b<11>1b<10>1b<9>1b<8>1b<7>1b<6>1b<5>1b<4>CLK_COR_SEQ_2_3_033<8>33<9>33<10>33<11>33<12>33<13>33<14>33<15>34<0>34<1>CLK_COR_SEQ_2_3_11c<7>1c<6>1c<5>1c<4>1c<3>1c<2>1c<1>1c<0>1b<15>1b<14>CLK_COR_SEQ_2_4_032<14>32<15>33<0>33<1>33<2>33<3>33<4>33<5>33<6>33<7>CLK_COR_SEQ_2_4_1
1d<1>1d<0>1c<15>1c<14>1c<13>1c<12>1c<11>1c<10>1c<9>1c<8>CLK_COR_SEQ_2_ENABLE_0
32<10>32<11>32<12>32<13>DRP Address by Attribute
FPGA可编程逻辑器件芯片XC2S15-6FGG256I中文规格书 - 图文
