FPGA可编程逻辑器件芯片XC2S30-5VQ100I中文规格书 - 图文

由天下分享时间：2024/12/4 7:45:30 加入收藏我要投稿点赞

Symbol

TIOTPHZ

Description

T input to Pad high-impedance

Speed Grade

-2I1.01

-1I1.12

-1M1.12

Unitsns

I/O Standard Adjustment Measurement Methodology

Input Delay Measurements

Table58 shows the test setup parameters used for measuring input delay.Table 58:Input Delay Measurement Methodology

Description

LVTTL (Low-Voltage Transistor-Transistor Logic)LVCMOS (Low-Voltage CMOS), 3.3VLVCMOS, 2.5VLVCMOS, 1.8VLVCMOS, 1.5VLVCMOS, 1.2V

PCI (Peripheral Component Interconnect), 33 MHz, 3.3V

PCI, 66 MHz, 3.3VPCI-X, 133 MHz, 3.3V

GTL (Gunning Transceiver Logic)

GTL PlusHSTL (High-Speed Transceiver Logic), Class I & IIHSTL, Class III & IVHSTL, Class I & II, 1.8VHSTL, Class III & IV, 1.8VSSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V

SSTL, Class I & II, 2.5VSSTL, Class I & II, 1.8V

AGP-2X/AGP (Accelerated Graphics Port)LVDS (Low-Voltage Differential Signaling), 2.5VLVDSEXT (LVDS Extended Mode), 2.5VLDT (HyperTransport), 2.5V

LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5VNotes:

1.2.3.4.5.6.

The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delaymeasurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all otherDCI standards are the same for the corresponding non-DCI standards.Input waveform switches between VL and VH.

Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREFvalues listed are typical.

Input voltage level from which measurement starts.

This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure11,page35.

The value given is the differential input voltage.

I/O Standard AttributeLVTTL

LVCMOS33LVCMOS25LVCMOS18LVCMOS15LVCMOS12PCI33_3PCI66_3PCIXGTL

GTLPHSTL_I, HSTL_IIHSTL_III, HSTL_IVHSTL_I_18, HSTL_II_18HSTL_III_18, HSTL_IV_18SSTL3_I,SSTL3_IISSTL2_I,SSTL2_IISSTL18_I,SSTL18_IIAGPLVDS_25LVDSEXT_25 LDT_25LVPECL_25VL(1)(2)

000000

VH(1)(2)

VMEAS

(1)(4)(5)VREF(1)(3)(5)–––––––––

3.01.43.31.652.51.251.80.91.50.751.20.6

Per PCI? SpecificationPer PCI SpecificationPer PCI-X? Specification

VREF–0.2VREF–0.2VREF–0.5VREF–0.5VREF–0.5VREF–0.5VREF–1.00VREF–0.75VREF–0.5VREF– (0.2xVCCO)1.2–0.1251.2–0.1250.6–0.1251.15–0.3VREF+0.2VREF+0.2VREF+0.5VREF+0.5VREF+0.5VREF+0.5VREF+1.00VREF+0.75VREF+0.5VREF+ (0.2xVCCO)1.2+0.1251.2+0.1250.6+0.1251.15–0.3VREFVREFVREFVREFVREFVREFVREFVREFVREFVREF0(6)0(6)0(6)0(6)

0.801.00.750.900.901.081.51.250.90AGP Spec

DS714 (v2.2) January 17, 2011Product Specification

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics

Output Delay Measurements

Output delays are measured using a Tektronix P6245

TDS500/600 probe (<1pF) across approximately 4\microstrip trace. Standard termination was used for all testing. The propagation delay of the 4\

characterized separately and subtracted from the final measurement, and is therefore not included in the

generalized test setups shown in Figure11 and Figure12.

X-Ref Target - Figure 11X-Ref Target - Figure 12FPGA Output+CREFRREFVMEAS–ds714_12_012109VREFFigure 12:Differential Test Setup

Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it.

Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method:

1.Simulate the output driver of choice into the generalized

test setup, using values from Table59.2.Record the time to VMEAS.

3.Simulate the output driver of choice into the actual PCB

trace and load, using the appropriate IBIS model or capacitance value to represent the load.4.Record the time to VMEAS.

5.Compare the results of step2 and step4. The increase

or decrease in delay yields the actual propagation delayof the PCB trace.

FPGA OutputRREFVMEAS(voltage level when taking delay measurement)CREF (probe capacitance)DS714_11_012109Figure 11:Single Ended Test Setup

Table 59:Output Delay Measurement Methodology

Description

LVTTL (Low-Voltage Transistor-Transistor Logic)LVCMOS (Low-Voltage CMOS), 3.3VLVCMOS, 2.5VLVCMOS, 1.8VLVCMOS, 1.5VLVCMOS, 1.2V

PCI (Peripheral Component Interface), 33 MHz, 3.3VPCI, 66 MHz, 3.3VPCI-X, 133 MHz, 3.3V

GTL (Gunning Transceiver Logic)GTL Plus

HSTL (High-Speed Transceiver Logic), Class IHSTL, Class IIHSTL, Class III

DS714 (v2.2) January 17, 2011Product Specification

I/O StandardAttribute

LVTTL (all)LVCMOS33LVCMOS25LVCMOS18LVCMOS15LVCMOS12

PCI33_3 (rising edge)PCI33_3 (falling edge)PCI66_3 (rising edge)PCI66_3 (falling edge)PCIX (rising edge)PCIX (falling edgeGTLGTLPHSTL_IHSTL_IIHSTL_III

RREF (?)1M1M1M1M1M1M2525252525252525502550

CREF(1)(pF)00000010(2)10(2)10(2)10(2)10(3)10(3)00000

VMEAS(V)1.41.651.250.90.750.60.942.030.942.030.942.030.81.0VREFVREF0.9

VREF(V)00000003.303.33.31.21.50.750.751.5

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics

DS714 (v2.2) January 17, 2011Product Specification

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics

DS714 (v2.2) January 17, 2011Product Specification

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics

Table 69:DSP48E Switching Characteristics (Cont’d)

Symbol

TDSPCCK_CEPP/TDSPCKC_CEPP

Description

CEP input to Pregister CLK

Speed Grade-2I0.630.01

-1I0.730.01

-1M0.730.01

Unitsns

Setup and Hold Times of the RST PinsTDSPCCK_{RSTAA, RSTBB}/TDSPCKC_{RSTAA, RSTBB}

TDSPCCK_RSTCC/ TDSPCKC_RSTCCTDSPCCK_RSTMM/ TDSPCKC_RSTMM DTSPCCK_RSTPP/TDSPCKC_RSTPP

{RSTA, RSTB} input to {A, B} register CLKRSTC input to Cregister CLKRSTM input to Mregister CLKRSTP input to Pregister CLK

0.28

0.260.210.210.290.210.630.01

0.330.310.260.280.360.260.730.01

nsnsnsns

Combinatorial Delays from Input Pins to Output PinsTDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M

{A, B} input to {P, CARRYOUT} output using multiplier

3.221.771.67

3.842.222.08

nsnsns

TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM {A, B} input to {P, CARRYOUT} output not

using multiplierTDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT}

{C, CARRYIN} input to {P, CARRYOUT} output

Combinatorial Delays from Input Pins to Cascading Output PinsTDSPDO_{AACOUT, BBCOUT}

TDSPDO_{APCOUT, ACRYCOUT,

AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M

TDSPDO_{APCOUT, ACRYCOUT,

AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM

TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT, CRYINPCOUT,

CRYINCRYCOUT, CRYINMULTSIGNOUT}

{A, B} input to

{ACOUT, BCOUT} output

{A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier{A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier{C, CARRYIN} input to {PCOUT,

CARRYCASCOUT, MULTSIGNOUT} output

1.123.22

1.313.84

nsns

1.922.422.42ns

1.822.282.28ns

Combinatorial Delays from Cascading Input Pins to All Output PinsTDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_M

TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_NM

TDSPDO_{ACINACOUT, BCINBCOUT} TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT,

BCINCRYCOUT, BCINMULTSIGNOUT}_M TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT,

BCINCRYCOUT, BCINMULTSIGNOUT}_NM

{ACIN, BCIN} input to {P, CARRYOUT} output using multiplier