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FPGA可编程逻辑器件芯片XC2S15-6FG456I中文规格书 - 图文

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Chapter4

User Primitives

The following configuration primitives are provided for users to access FPGA configuration resources during or after FPGA configuration.

BSCAN_VIRTEX5

JTAG is a standard four-pin interface: TCK, TMS, TDI, and TDO. Many applications are built around this interface. The JTAG TAP controller is a dedicated state machine inside the configuration logic. BSCAN_VIRTEX5 provides access between the JTAG TAP controller and user logic in fabric. There are up to four instances of BSCAN_VIRTEX5 for each device, each instance is controlled with the JTAG_CHAIN parameter. Table4-1 lists the BSCAN_VIRTEX5 fabric pins.

Table 4-1:BSCAN_VIRTEX5 Pin TablePin Name SEL

TypeOutput

Description

Active-High interface selection output. SEL=1 when the JTAG instruction register holds the corresponding USER1-4

instruction. Change in Update_IR state. SEL changes on the falling edge of TCK in the UPDATE_IR state of the TAP controller.

Active-High reset output. RESET=1 during the TEST-LOGIC-RESET state, PROGRAM_B, or during power up. This signal is deasserted on the falling edge of TCK.Fed through directly from the FPGA TDI pin.

DRCK is the same as TCK in the Capture_DR and Shift_DR states. If the interface is not selected by the instruction register, DRCK remains High.

Active-High pulse indicating the Capture_DR state. This signal is asserted on the falling edge of TCK.

Active-High pulse indicating the Update_DR state. This signal is asserted on the falling edge of TCK.

Active-High pulse indicating the Shift_DR state. This signal is asserted on the falling edge of TCK.

TDO input driven from the user fabric logic. This signal is internally sampled on the falling edge before being driven out to the FPGA TDO pin.

RESETOutput

TDIDRCK

OutputOutput

CAPTUREUPDATESHIFTTDO

OutputOutputOutputInput

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Dynamic Reconfiguration of Functional Blocks

is presented simultaneously with the write address and DWE and DEN signals prior to the next positive edge of DCLK. The port asserts DRDY for one clock cycle when it is ready to accept more data. The timing requirements relative to DCLK for all the other signals are the same. The output data is not registered in the functional blocks. Output (read) data is available after some cycles following the cycle that DEN and DADDR are asserted. The availability of output data is indicated by the assertion of DRDY.

Figure5-4 and Figure5-5 show the timing relationships between the port signals for write and read operations. Absolute timing parameters, such as maximum DCLK frequency, setup time, etc., are defined in DS202, Virtex-5 Data Sheet: DC and Switching Characteristics.

DCLKDENDRDYDWE

DADDR[m:0]

DI[n:0]DO[n:0]

UG191_c5_04_050406

bbBB

Figure 5-4:Write Timing with Wait States

DCLKDENDRDYDWE

DADDR[m:0]

DI[n:0]DO[n:0]

AA

UG191_c5_05_050406

AA

Figure 5-5:Read Timing with Wait States

Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020

Chapter 6:Configuration Details

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Chapter 7:Readback and Configuration Verification

Table 7-2:Step12

Shutdown Readback Command Sequence (SelectMAP) (Continued)SelectMAP PortDirection

Write

Configuration Data

30008001000000052000000030008001

Explanation

Type 1 Write 1 Word to CMDSTART CommandType 1 NOOP Word 0Type 1 Write 1 Word to CMDRCRC CommandType 1 NOOP Word 0Type 1 Write 1 Word to CMDDESYNCH CommandType 1 NOOP Word 0Type 1 NOOP Word 0

13Write

0000000720000000

1415

WriteWrite

300080010000000D2000000020000000

User logic should strobe readback data while DOUT_BUSY is Low after switching from a write to a read (both CS_B and RDWR_B are Low). DOUT_BUSY must be monitored to determine when the readback data is valid.

When readback is initiated, and after BUSY is deasserted, 42 dummy words are read back. In x16 and x8 modes, the readback cycles multiply by 2 and 4 respectively.Table 7-3:Readback DOUT_BUSY Latency (SelectMAP)

x8

Read to DOUT_BUSY Latency

Notes:

These latencies assume CS_B is deasserted for one cycle when changing from write to read (RDWR_B deassertion). It is best to monitor the BUSY signal for valid readback data.

x163 clocks

x324 clocks

1 clock

Accessing Configuration Registers through the JTAG Interface

JTAG access to the Virtex-5 configuration logic is provided through the JTAG CFG_IN and CFG_OUT registers. The CFG_IN and CFG_OUT registers are not configuration registers, rather they are JTAG registers like BYPASS and BOUNDARY_SCAN. Data shifted into the CFG_IN register go to the configuration packet processor, where they are processed in the same way commands from the SelectMAP interface are processed.

Readback commands are written to the configuration logic by going through the CFG_IN register; configuration memory is read through the CFG_OUT register. The JTAG state transitions for accessing the CFG_IN and CFG_OUT registers are described in Table7-4.

Table 7-4:Step

1234

Shifting in the JTAG CFG_IN and CFG_OUT Instructions

Description

Set and HoldTDI

XXXX

TMS

1010

# of Clocks (TCK)

5122

C lock five1s on TMS to bring the device to the TLR stateMove into the RTI stateMove into the Select-IR stateMove into the Shift-IR State

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Chapter 9:Readback CRC

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

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