BES2300-Z Product Specification
VINLinear Battery ChargerVBATBES200-A
Figure 2-13 BES2300-Z External Charge Connection
When choosing a battery charger, please follow the guide below:
Higher input voltage tolerance alleviates the concerns of the AC adaptor USB bus spiking during disconnection or connection scenarios.
When VIN is disconnected, leakage current still flows from battery to charger. The lower leakage current from battery makes longer system standby time.
The Li-ion battery charger has at least three phases of charging: Pre-charge to recover a fully discharged battery, constant current charge to supply the charge safely and constant voltage regulation to safely reach full capacity. Figure 2-9 shows the mode-to-mode transition of the charger.
Charge Voltage &CurrentVBAT=4.2vVRCHIccIpreItermt
Figure 2-14 The Mode-to-mode Transition of The Charger
BES2300-Z Product Specification
2.11 Audio Interface
Codec includes filter for analog frontend, accelerator for audio processing algorithm, ANC supporting avoiding music cancel, and host interface. CODECD works with CODECA or digital microphone. The audio interface circuit consists of: ? ? ? ? ? ?
Stereo/dual-mono audio codec
There 24-bit high-quality ADC channels with sample rates from 8 KHz to 384 KHz Two 24-bit high-quality DAC channels with sample rates from 8 KHz to 384 KHz One low power ADC and voice detection unit for VAD application SPDIF interface 1 input and 1 output 1 configurable I2S interface
ADC0Codec FilterDMA interface for ADCADC1Codec FilterADC2Codec FilterANCConfig interface DAC0Codec FilterDMA interface for DACDAC1Codec FilterAccelerator for EQ/Aduio processingDMA interface for ACC
Figure 2-15 BES2300-Z Audio Codec Diagram
2.11.1 ADCI2SFunction The I2S bus consists of a serial data in line (SDI), a serial data out line (SDO), a word select line (WS), and a serial clock (SCLK). The serial data line is time multiplexed to allow the transfer of two data streams (such as, left and right stereo data).
Apb_i2s module has the following features: 1) APB data bus width of 32 bits
2) I2S transmitter and/or receiver based on the Philips I2S serial protocol
3) Full duplex communication due to the independence of transmitter and receiver 4) Asynchronous clocking of APB bus and I2S SCLK 5) Master or slave mode of operation
BES2300-Z Product Specification
6) Audio data resolutions of 12, 16, 20, 24, and 32 bits 7) External SCLK gating and enable signals 8) FIFO depth of 8 words with wordsize of 32 bits 9) Programmable FIFO thresholds
10) Configurable support for programmable DMA registers
Diagram Figure 2-6 shows the block diagram of apb_i2s module.
sclkpclkpclk domainsclk domainSCLKpaddrI2S ClockGenerationtx_dataWSpwdataAPBInterfacetx_intrTX FIFOI2STransmitterBlockSDOprdatatx_cfgI2SRegisterBlockdma_reqrx_dataSyncsclk_intws_intdma_ackI2S DMAInterfacerx_intrRX FIFOI2SReceiverBlockSDIrx_cfginterruptsSync
Figure 2-16 BES2300-Z Apb_i2s Block Diagram
Interface Timing Diagram Apb_i2s supports the standard I2S frame format for transmitting and receiving data —the MSB of a word is sent one SCLK cycle after a word select change. This format is illustrated in Figure 7-3-2. Serial data sent by the transmitter
is synchronized with the negative edge of the SCLK signal. The receiver latches the serial data on the rising edge of SCLK.
BES2300-Z Product Specification
sclkwsdataMSBLeftRightLSBMSB
Figure 2-17 BES2300-Z I2S Stereo Frame Format
2.11.4 PDM
Function The PDM (Pulse Density Modulation) interface is used to connect the MEMS (Micro-Electrical-Mechanical System) microphone and the codec module. It multiplexes with the analog microphone input, uses the codec module’s decimation filter to decode the PDM stream bits.
The PDM interface consists of a PDM data in line, a PDM clock out line, both of which are multiplexed in GPIO. There are 3 PDM interfaces in the codec module, each of which can transfer data on either edge of the PDM clock, thus enough to supply data for the 5 digital ADC channels in the codec module concurrently. Diagram pdm_datapdm_clkPdm InterfaceMUXCodec FilterTo Codec
adc_inputCodec FilterFigure 2-18 BES2300-Z PDM Interface in Codec
Interface Timing diagram The PDM clock frequency is 1/4 of the codec ADC clock. Data can be transferred on either edge of the PDM clock, thus the single data line can transfer stereo data. Codec use ADC clock to sample the data, the capture phase can be configured. Figure 7-4-2 shows the PDM interface timing.
BES2300-Z Product Specification
pdm_clkpdm_data
Figure 2-19 BES2300-Z PDM timing
BES2300
