BES2300

BES2300-Z Product Specification

? AONGPIO module sends out a combined interrupt to CPU.

For edge interrupt, interrupt signal that sent out has been synchronized to apb-bus clock; for level interrupt, if synchronized depends on configuration. Because all system interrupts has already been synchronized in CPU, if synchronized in GPIO module is not a problem Protocol Timing

2.9.6 LED DRIVERS 2.9.7 GPADC

2.9.8 SDIO/EMMC

BES2300-Z has a SDMMC module to support SD or SDIO or eMMC interface, with CLK, CMD, and DATA [7:0] signals. BES2300-Z works as host controller to connect external mass storage SD card, or various function SDIO device, or mass storage eMMC chip. BES2300-Z supports up to SDR25/4-bit/version 3.0 for SD, or SDR25/4-bit/version 3.0 for SDIO, or SDR/52MHz/8-bit/version 4.41 for eMMC. BES2300-Z could support only one interface from SD/SDIO/eMMC at a time, and could support only one card/device/chip. Features of SD/SDIO/eMMC interface: ? ? ? ? ? ? ? ? ? ? ? ?

Interface controller is on AHB bus, with ahb-bus clock and module clock. Module clock is OSC or OSCX2. FIFO based design, with 16x32 TX FIFO and 16x32 RX FIFO. FIFO trigger threshold could be configured. Support DMA to transfer data on AHB bus.

Support interrupt to report events and errors, such as FIFO, response timeout, CRC error, etc. Works as host controller to support SD or SDIO or eMMC interface.

Supports up to SDR25/4-bit/version 3.0 for SD, or SDR25/4-bit/version 3.0 for SDIO, or SDR/52MHz/8-bit/version 4.41 for eMMC.

Support only one interface from SD/SDIO/eMMC at a time, and support only one card/device/chip.

Programmable interface clock frequency. Max interface clock frequency is 52MHz, when module clock is OSCX2. Support 1-bit/4-bit DATA for SD/SDIO; support 1-bit/4-bit/8-bit DATA for eMMC. Support clock stop when TX FIFO is empty or RX FIFO is full, to avoid data loss. Support SDIO suspend and resume operation. Support SDIO read wait.

Support block size of 1 to 65,535 bytes. And support multi-block transfer.

Application Notes Hold timing of host output signals, including CMD and DATA output, could be configured by driver. Sampling phase of host input signals, including CMD and DATA input, could also be configured by driver. Following is description on this for clarity. Interface Timing: BES2300-Z Product Specification

Recommendation of frequency ratio between module clock and interface CLK signal is 1:1. That is, internal clock divider is bypassed, CLKDIV=0. The wanted interface CLK frequency comes from CMU settings. If want to use 90 degree or 270 degree of internal CLK for hold timing or sampling phase, the frequency ratio between module clock and interface CLK signal needs to be 2:1. That is, internal clock divider is used, CLKDIV=1. Otherwise, 90 degree and 270 degree don’t exist.

Driver could get proper timing configuration after training. Following example is 1:1 ratio. 1) Host output hold timing Set use_hold_reg=1 in CMD register to guarantee hold timing. Select delay version of interface CLK (180 degree) to register CMD/DATA output with hold_reg. If skew between CLK and CMD/DATA on cardbus is not more than half a cycle, it’s safely for card to sample CMD/DATA. 2) Host input sampling phase Set SELECT_PRESAMPLE=1 in CLKSRC register to presample CMD/DATA input, with 0 degree interface CLK. Firstly, presample CMD/DATA input; then the presampled values will be registered by negedge of module clock; and then registered by posedge of module clock.

2.1) If card outputs CMD/DATA by negedge of CLK (SD 2.0 standard)

If “host CLK out to CMD/DATA input” round trip delay <0.25T, please enable presample; if 0.25T< round trip delay <0.75T, please bypass presample, and sample CMD/DATA with negedge of module clock directly; if round trip delay >0.75T, please lower down CLK frequency.

2.2) If card output CMD/DATA by posedge of CLK (SD 3.0/SDIO 3.0/eMMC 4.41 standard)

If “host CLK out to CMD/DATA input” round trip delay <0.75T, please enable presample; if 0.75T< round trip delay <1.25T, please bypass presample, and sample CMD/DATA with negedge of module clock directly; if round trip delay >1.25T, please lower down CLK frequency.

(Here already reserve 0.25T setup time for above maximum acceptable round trip delay 0.75T/1.25T. If not reserve setup time, the maximum acceptable round trip delay will be 1T/1.5T.) Related CLKSRC register bit: Table 2-7 Some of CLKSRC register bits

BIT NAME FUNCTION 28 CCLK_DRV_SEL Hold_reg clock select. BES2300-Z Product Specification

0: select CCLK_out_phase90 1: select CCLK_out_phase180 Default 1. 25 SELECT_PRESAMPLE If use presample register. Presample register is for hold timing. 0: not use presample register, directly sampling data from cardbus. 1: use presample register. Sampling data from presample register. Default 1. 24 CCLK_PRESAMPLE_SEL Presample clock select. 0: select CCLK_out_phase270 1: select CCLK_out_phase0 (=phase360) Default 1.

Protocol Timing

In Figure 6-7 and 6-8, the clock is representative only and does not show the exact number of clock cycles.

Figure 2-10 Multiple-Block Read Operation

BES2300-Z Product Specification

Figure 2-11 Multiple-Block Write Operation

2.9.9 USB

2.10 Power Control and Regulation

BES2300-Z integrates Power Management Unit (PMU), which supports 3.1V~5.5V input for VBAT, DCXO with internal oscillator circuit, power on reset control, internal 32KHz OSC for standby and sleep state, internal LPOs supporting for low power mode.

BES2300-Z offers various low power features to reduce system consumption. Features include standby mode with 32 KHz clock, power down mode for individual peripherals and processor sleep mode. In addition, BES2300-Z is also fabricated using the advanced low leakage CMOS process in order to provide ultra-low leakage solution.

2.10.1 INTERNAL POWER CONTROL AND REGULATION

For power efficiency consideration, BES2300-Z includes 3 switch-mode regulator (SMR). One of the SMR generates a 1.8V supply rail with 200mA output currents; another one generates a 1.3V supply rail with 200mA output currents; another one generates a 0.9V supply rail with 200mA output currents. BES2300-Z also includes 7 linear regulators (LDOs):

LDO_MEM generates a 1.2~2.8V supply rail for on-chip memory; LDO_USB generates a 2.4~3.9V supply rail for USB2.0 interface; LDO_VIO generates a 1.2~3V supply rail for the general purpose IOs; LDO_CODEC generates a 1.2~3.7V supply rail for the Codec units;

LDO_ANA generates a 1.2~2.7V supply rail for the analog building blocks on-chip; LDO_CORE generates 0.6~1.35V supply rail for the digital logics.

There are three switch-mode configurations for the on-chip PMU. A 1.8V, 1.3V and 0.9V three-supply rail system as illustrated in Figure 2-4:

BES2300-Z Product Specification

0.3-4.4(1.3V)buck_ana200mA(max)0.3-2.7(1.3V)ldo_ana_buck200mA(max)vana_buck 1.3V/1.4V

crystal10mA(max)RF50mA(max)vana_buck 1.3V/1.4V1.1-1.6(1.3V)ldo_buck2anadefault bypassvana 1.3VRFPA50mA(max)0.3-4.4(0.9V)buck_core200mA(max)0.3-1.5(0.9V)vcore 0.9Vcore100mA(max)vana_buck 1.3V/1.4Vldo_core200mA(max)0.3-1.5(0.9V)ldo_vbat2core200mA(max)0.3-4.4(1.9V)vbatbuck_hppa200mA(max)0.6-3.6(1.9V)vhppa 1.9Vdifferentialhppa125mA(max)ldo_hppa200mA(max)vhppa 1.9Vldo_hppa2co1.2v-2.7vvcodec 1.8Vdec200mA(max)codecdac adc20mA(max)1.2-2.7(1.8V)ldo_codec200mA(max)1.2-4.3(2.8V)flash50mA(max)ldo_vio200mA(max)1.2-2.7(1.8V)vio 2.8Vgpio100mA(max)ldo_mem200mA(max)2.4-3.9(3.3V)vmem 1.8Vmem100mA(max)ldo_usb200mA(max)vusb 3.3Vusb100mA(max)Figure 2-12 BES2300-Z Chip Power Rail

2.10.2 EXTERNAL CHARGER CONFIGURATION

An external Li-ion battery charger is needed for BES2300. Typically, a linear charger up to 200mA charge current is suitable for a wide range of applications. Figure 2-8 illustrates the connection between external charger and BES2300.