BES2300

BES2300-Z Product Specification

Receive DMA includes single character DMA transfer and burst DMA transfer, with burst threshold of receive FIFO configured in UARTIFLS register. Transmit DMA includes single character DMA transfer and burst DMA transfer, with burst threshold of transmit FIFO configured in UARTIFLS register.

Table 2-6 Burst threshold of receive and transmit FIFO

In addition to the above, the DMAONERR bit in the DMA control register supports the use of the receive error interrupt, UARTEINTR. It enables the DMA receive request to be masked out when the UART error interrupt, UARTEINTR, is asserted. The DMA receive request outputs remain inactive until the UARTEINTR is cleared. The DMA transmit request outputs are unaffected. Protocol Timing

Figure 2-5 UART interface protocol timing

2.9.2 SPI

BES2300-Z has two independent SPI master interfaces: SPI0 and SPI1. Features of these interfaces are same. These SPI interfaces are master interface to support Motorola SPI-compatible interface, and each could connect up to three SPI slave interfaces with separate CS (chip select) and DI (data in) signals. These SPI interfaces also support SPI serial display interface with D/C (data or command distinguish) signal. Features of SPI interface: ? ? ? ?

Interface controller is on APB bus, with apb-bus clock and module clock. Module clock is OSC or OSCX2. FIFO based design, with 8x32 TX FIFO and 8x32 RX FIFO.

Support DMA to transfer data on APB bus. (FIFO threshold is 4 in DMA mode.)

Support interrupt to report events and errors, such as FIFO, RX overrun, RX timeout, etc.

BES2300-Z Product Specification

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Programmable bitrate generator. This enables division of the module clock by 2~254 to generate an internal clock, which is divided by further 1~256 to generate bitrate. Max bitrate is 52MHz/2=26MHz.

Motorola SPI-compatible master interface. Full duplex, four-wire synchronous transfers, and programmable clock polarity and phase.

Programmable data frame size from 4 to 32 bits.

Support up to three SPI slave interfaces with separate CS (chip select) and DI (data in) signals.

Support SPI serial display interface with D/C (data or command distinguish) signal.

Protocol Timing

The Motorola SPI interface is a four-wire interface where the SPI_CS signal behaves as a slave select. The main feature of the Motorola SPI format is that the inactive state and phase of the SPI_CLK signal are programmable through the SPO and SPH bits within the SSPSCR0 control register. SPO (clock polarity) When the SPO clock polarity control bit is LOW, it produces a steady state low value on the SPI_CLK pin. If the SPO clock polarity control bit is HIGH, a steady state high value is placed on the SPI_CLK pin when data is not being transferred.

SPH (clock phase) The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is LOW, data is captured on the first clock edge transition. If the SPH clock phase control bit is HIGH, data is captured on the second clock edge transition.

Figure 2-6 Motorola SPI frame format with SPO=0 and SPH=0

BES2300-Z Product Specification

2.9.2 I2C

BES2300-Z has two independent I2C master interfaces: I2C0 and I2C1. Features of these interfaces are same. These I2C interfaces are master interface to support two-wire I2C serial interface with SCL (clock) and SDA (data) signals. Features of I2C interface: ? ? ? ? ? ? ?

Interface controller is on APB bus, with apb-bus clock and module clock. Module clock is OSC or OSCX2, or internal LPO 32 kHz.

FIFO based design, with 8x11 TX FIFO and 8x8 RX FIFO. FIFO trigger threshold could be configured. Support DMA to transfer data on APB bus. Support interrupt or polled-mode operation. Support bulk transmit mode.

Support interrupt to report events and errors, such as FIFO, RX overrun, TX underrun, TX abort, etc. Programmable I2C clock frequency. Max I2C clock frequency is 52MHz/(22+14)=1.44MHz， when module clock is OSCX2.

(If need higher I2C clock frequency, please contact FAE for details.) ? ? ? ?

Support three I2C speeds: Standard mode (0 to 100Kb/s); Fast mode (up to 400Kb/s); Fast mode Plus (up to 1.4Mb/s). Support RESTART.

Support 7-bit or 10-bit addressing. Support spike suppression for SDA.

Programmable SDA hold time.

Protocol Timing

The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to perform wire-AND functions on the bus. Data is transmitted in byte packages.

Figure 2-7 Data transfer on the I2C Bus

BES2300-Z Product Specification

2.9.3 AONPWM

BES2300-Z has a PWM interface in AON subsystem. The PWM interface includes four PWM_OUT signals, which could output square waveform. Frequency and duty cycle of the square waveform could be programmed independently for these four PWM_OUT. Besides square waveform function, PWM_OUT2 and PWM_OUT3 also support hardware “breathing LED” function, to remove CPU loading in software solution. Features of AONPWM interface: ? ? ? ?

Interface controller is on AONAPB bus, with apb-bus clock and module clock. Module clock is OSC or internal LPO 32 kHz.

Support four PWM_OUT signals, which could output square waveform independently.

Programmable PWM_OUT frequency. Max frequency is 26MHz/2=13MHz, Min frequency is 32 kHz/65536=0.5Hz.

Programmable PWM_OUT duty cycle. Duty cycle is 0~1, granularity is 1/65536.

PWM_OUT2 and PWM_OUT3 also support hardware “breathing LED” function. The breath curve could be partially programmed.

Protocol Timing

Figure 2-8 PWM_OUT square waveform timing diagram

2.9.4 PMUPWM

BES2300-Z has a PWM module in PMU subsystem, to add PWM function on LED Pins (LED0/1). The PWM module includes two PWM_OUT signals, which could output square waveform. Frequency and duty cycle of the square waveform could be programmed independently for these two PWM_OUT. Besides square waveform function, these two PWM_OUT also support hardware “breathing LED” function, to remove CPU loading in software solution.

If PWM function in PMU is enabled, these two PWM_OUT will apply onto LED0 and LED1, respectively. If PWM function in PMU is disabled, two programmable register bit value will apply onto LED0 and LED1, respectively. Features of PMUPWM module: ? ?

PMUPWM module is in PMU subsystem, and module clock is internal LPO 32 kHz. Support two PWM_OUT signals, which could output square waveform independently.

BES2300-Z Product Specification

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Programmable PWM_OUT frequency. Max frequency is 32 kHz/2 = 16 kHz, Min frequency is 32 kHz/65536=0.5Hz.

Programmable PWM_OUT duty cycle. Duty cycle is 0~1, granularity is 1/65536.

These two PWM_OUT also support hardware “breathing LED” function. The breath curve could be partially programmed.

Protocol Timing

Figure 2-9 PWM_OUT square waveform timing diagram

2.9.5 GPIO

BES2300-Z has a GPIO module in AON subsystem. The GPIO module supports 32 programmable general purpose IOs. Direction and output data of these IOs could be programmed separately and independently. Input data of these IOs, which are synchronized to apb-bus clock, could be read back through memory-mapped register.

The 32 IOs all support interrupt. Interrupt features could be programmed separately and independently for these IOs. Features include interrupt type (level or edge), polarity (active-high/low, rising/falling-edge), mask enable and debounce enable. The interrupt function only works when direction is input for an IO. GPIO module sends out a combined interrupt to CPU, so programmer needs to select current interrupt source IO with interrupt status register in ISR (interrupt service routine).

BES2300-Z has 32 digital pads. GPIO function and other alternate functions (for example, uart, SPI, etc.) are multiplexed on these digital pads. That is, each digital pad has above GPIO and interrupt function. (Please note, NOT all digital pads are packaged out.)

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AONGPIO module is on AONAPB bus, with apb-bus clock and debounce clock (internal LPO 32 kHz).

Support 32 programmable general purpose IOs, direction and output data of these IOs could be programmed separately and independently.

Input data of these IOs, which are synchronized to apb-bus clock, could be read back through memory-mapped register.

Reset direction is input for these IOs.

The 32 IOs all support interrupt. Interrupt features could be programmed separately and independently. Interrupt features include interrupt type (level or edge), polarity (active-high/low, rising/falling-edge), mask enable and debounce enable.

Support optional debounce in interrupt function, with 32 kHz debounce clock. If enable debounce, interrupt signal will delay two 32 kHz cycles.