BES2300

BES2300-Z Product Specification

4 Timer 0x4008_4000 0x4008_4FFF ARM 5 PSC 0x4008_5000 0x4008_5FFF BES 6 IOMUX 0x4008_6000 0x4008_6FFF BES 7~15 Reserved 0x4008_7000 0x4008_FFFF

2.4 Interrupt

2.5 DMA

2.6 Timers

2.7 HWI2C

2.8 CMU

2.9 System Peripherals

BES2300-Z is embedded with necessary peripheral blocks, and supports UART or USB download. ? ? ? ? ? ? ? ? ?

Clock Management Unit (CMU) provides general controls over the whole system UART with configurable baud rate I2C master/slave peripheral interface

General Purpose Input Output (GPIO) with independent interruptions Pulse Width Modulation (PWM)

Several timers: RTC timer, WDT, general purpose timer USB 2.0 HS device and USB Type C compliant Sony/Philips Digital Interface Format (SPDIF)in/out Real Time Clock (RTC)

BES2300-Z Product Specification

2.9.1 UART

BES2300-Z has three independent UART interfaces: UART0, UART1 and UART2. UART0 is used for flash download purpose when chip is configured as uart-download mode in EFUSE. UART1 has hardware flow control signals, but UART0 and UART2 have not. Besides above two things, features of these UART interfaces are same. Features of UART interface:

? ? ? ? ?

Interface controller is on APB bus, with apb-bus clock and module clock. Module clock is OSC or OSCX2.

FIFO based design, with 16x8 TX FIFO and 16x12 RX FIFO. FIFO trigger threshold could be configured. Support DMA to transfer data on APB bus.

Support interrupt to report errors, such as overrun, underrun, RX timerout, etc.

Programmable baudrate generator. This enables division of the module clock by 1~65535 to generate an internal x16 clock, which is 16 times of baudrate. The divisor can be a fractional number. Max baudrate is 52MHz/16=3.25MHz. ? ? ? ?

Standard asynchronous communication bits (start, stop and parity). These are added prior to transmission and removed on reception. False start bit detection.

Line break generation and detection. Programmable hardware flow control.

Fully-programmable serial interface characteristics: data can be 5, 6, 7, or 8 bits; even, odd, stick, or no-parity bit generation and detection; 1 or 2 stop bit generation. Block Diagram BES2300-Z Product Specification

Figure 2-4 BES2300-Z UART interface controller block diagram

UART Operation Control data is written to UART line control register, UARTLCR_H. This register is 29 bits wide internally, but is externally accessed through APB bus by writes to three register locations, UARTLCR_H, UARTIBRD, and UARTFBRD. UARTLCR_H defines: ? transmission parameters ? word length ? buffer mode

? number of transmitted stop bits ? parity mode

BES2300-Z Product Specification

? break generation

UARTIBRD and UARTFBRD together define the baudrate divisor.

Fractional baudrate divider The baudrate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. This is used by the baudrate generator to determine the bit period. The fractional baudrate divider enables to generate all the standard baudrates.

The 16-bit integer is loaded through the UARTIBRD register. The 6-bit fractional part is loaded through the UARTFBRD register. The Baudrate Divisor has the following relationship to UARTCLK: Baudrate Divisor = UARTCLK/ (16xBaudrate) = BRDI + BRDF

Where BRDI is the integer part and BRDF is the fractional part, separated by a decimal point as (BRDI.BRDF). You can calculate the 6-bit number (m) by taking the fractional part of the required baudrate divisor and multiplying it by 64 and adding 0.5 to account for rounding errors: m = integer (BRDF * 64 + 0.5)

Data transmission or reception Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information.

For transmission, data is written into the transmit FIFO. If UART is enabled, it causes a data frame to start transmitting with the parameters indicated in UARTLCR_H. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. BUSY can be asserted HIGH even though UART might no longer be enabled.

For reception, when the receiver is idle (UARTRXD continuously 1), and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and data is sampled on the eighth cycle of that counter in normal UART mode.

The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is,

BES2300-Z Product Specification

one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled.

Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word (see Table 6-1).

Table 2-5 Receive FIFO bit functions

Three error bits are stored in bits [10:8] of the receive FIFO, and are associated with a particular character. There is an additional error that indicates an overrun error and this is stored in bit 11 of the receive FIFO. The overrun bit is not associated with the character in the receive FIFO. The overrun error is set when the FIFO is full, and the next character is completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. When an empty location is available in the receive FIFO, and another character is received, the state of the overrun bit is copied into the receive FIFO along with the received character. The overrun state is then cleared.

Hardware Flow Control The hardware flow control feature is fully selectable, and enables you to control the serial data flow by using the nUARTRTS output and nUARTCTS input signals.

When the RTS flow control is enabled, the nUARTRTS signal is asserted until the receive FIFO is filled up to the programmed watermark level. When the CTS flow control is enabled, the transmitter can only transmit data when the nUARTCTS signal is asserted. The hardware flow control is selectable through bits 14(RTSEn) and 15(CTSEn) in the UART control register (UARTCR) DMA Interface UART provides an interface to connect to DMA controller. DMA operation of the UART is controlled through the UART DMA control register, UARTDMACR.