BES2300

BES2300-Z Product Specification

Figure 2-1 Platform Architecture ................................................................................................................................ 10 Figure 2-2 BES2300-Z the Interaction between the Sub-systems ............................................................................... 11 Figure 2-3 BES2300-Z System Address Map .............................................................................................................. 13 Figure 2-4 BES2300-Z UART interface controller block diagram ............................................................................... 18 Figure 2-5 UART interface protocol timing ............................................................................................................. 21 Figure 2-6 Motorola SPI frame format with SPO=0 and SPH=0 ................................................................................ 22 Figure 2-7 Data transfer on the I2C Bus ..................................................................................................................... 23 Figure 2-8 Multiple-Block Read Operation ................................................................................................................ 28 Figure 2-9 Multiple-Block Write Operation ............................................................................................................... 29 Figure 2-10 BES2300-Z Chip Power Rail ..................................................................................................................... 30 Figure 2-11 BES2300-Z External Charge Connection ................................................................................................. 31 Figure 2-12 The Mode-to-mode Transition of The Charger ...................................................................................... 31 Figure 2-5 BES2300-Z Audio Codec Diagram ............................................................................................................. 32 Figure 2-14 BES2300-Z Apb_i2s Block Diagram ......................................................................................................... 33 Figure 2-15 BES2300-Z I2S Stereo Frame Format ...................................................................................................... 34 Figure 2-16 BES2300-Z PDM Interface in Codec ........................................................................................................ 34 Figure 2-17 BES2300-Z PDM timing ........................................................................................................................... 35 Figure 3-1 Bluetooth transceiver architecture .......................................................................................................... 37 Figure 3-2 Digital PHY Architecture ........................................................................................................................... 38 Figure 3-3 the signal flow of the digital PHY receiver ............................................................................................... 39 Figure 3-4 Digital PHY Transmitter Parts ................................................................................................................... 39 Figure 3-5 Bluetooth top-level diagram .................................................................................................................... 40 Figure 3-6 Bluetooth data path .................................................................................................................................. 41 Figure 5-7 BLE data path ............................................................................................................................................ 41 Figure 5-1 BES2300-Z Pins ........................................................................................................................................... 50

BES2300-Z Product Specification

Figure 6-1 BES2300-Z Dimension ................................................................................................................................ 54 Figure 7-1 Solder Reflow Profile ................................................................................................................................. 55 Figure 9-1 Tape Orientation ........................................................................................................................................ 59 Figure 9-2 Reel Dimensions (All dimensions in millimeters) ....................................................................................... 59 Figure 9-3 Tape Dimensions (All dimensions in millimeters) ...................................................................................... 60

Rev 1.0 Page7 / 60 Confidential and Proprietary – Bestechnic (Shanghai) Co., Ltd

BES2300-Z Product Specification

1 General Description

BES2300-Z is a highly integrated SoC with Bluetooth 5.0 dual mode and high performance Cortex-M4F for wireless audio and voice application. It is also optimized for FWS (Fully Wireless Stereo) application, which is BES’s stereo connection technology between primary and secondary Voice Box.

BES2300-Z minimizes the external components and BOM cost by highly integrating RF transceiver, high performance audio codec and Cap-less headphone driver. It also integrates serial Flash and powerful Cortex-M4F MCU to support various software features and product customization. BES2300-Z is manufactured with advanced low power CMOS process and assembled with a 4.5*6.2mm 80-ball BGA package.

DC/DCMCUBT_RFBTMAC/PHY ADCLDOFLASHConnectivity/StorageCRYSTALROM/RAMPeripheralCODEC DIGDAC_LDAC_R Figure 1-1 BES2300-Z Top View

1.1 Applications

? ? ? ? ? ?

High-end FWS headset High-end Bluetooth headset Smart BT/WIFI music box BT boom box

Other portable audio device IOT platform

BES2300-Z Product Specification

1.2 Features

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

CMOS Single-chip Fully-integrated RF, PMU, Audio CODEC and Cortex-M4F CPU Bluetooth 5.0 dual mode

Integrated near field transceiver for voice and music with low absorption by human body Up to 300MHz ARM Cortex-M4F Processor 4MB Serial Flash On-chip for Custom Program Cortex-M4F with On-chip Boot-ROM and RAM Security Boot to Protect Custom IP 3.1V-5.5V Input for VBAT Internal LPO for Low Power Mode. DCXO with Internal Oscillator Circuit Support FWS

Dual MICs Noise Reduction Echo Cancellation USB 2.0 HS device

Support low power voice activity detection Multi-band EQ and Bass enhancement Immersive audio with 3D or virtual surround sound

Support Active Crossover

? ? ? ? ? ? ?

? Crossover filter: DSP Adjustable ? Active Crossover Two-way application:

Sports Bluetooth & FWS Bluetooth Support Talk through Support Temperature Sensor Support Class H 24-bit Audio Processing Support USB Audio Playback HiFi Stereo Audio DAC: ? 120dB SNR ? 110dB DNR

? Supports Rates From 8 KHz to 384 KHz HiFi Stereo Audio ADC: ? 100dB SNR

? Supports Rates From 8 KHz to 384 KHz ? Support dual/single Mic noise

suppression and ANC ? Support ambient awareness ? 3D recording

BES2300-Z Product Specification

2 Platform Feature

BES2300-Z is designed for high-resolution wireless audio MCU system as shown in Figure 2-1.

AHB2APBCortex-M4FSRAMAHBUARTI2CAPBCMUCODECPCMWDTPWMBT 5.0MACPHYBOOT ROMFLASHDMA1SPI1GPIOGPADCTIMER

Figure 2-1 Platform Architecture

2.1 MCU Subsystem

BES2300-Z is embedded with the ARM Cortex-M4F processor, which provides best trade-off between system performance and power consumption. For large amount of data transfer, high performance Direct Memory Access (DMA) is implemented, which greatly enhances the data movement speed while reducing MCU processing load. ? ? ? ? ? ? ? ? ? ? ?

Cortex-M4F high performance processor with float and HW DSP instruction High performance multi-layer AMBA bus Operating frequency up to 300MHz Security boot support

MCU provides computing power for RTOS, BT profile, audio processing and user program. High bandwidth modules are connected by multi-layer AHB bus, such as CPU/DMA/memories; low bandwidth modules are put on APB bus, such as UART/I2C/SPI.

AHB bus frequency and APB bus frequency could be different. Besides bus clock, some modules have module clock, which could differ with bus clock.

CPU core is ARM Cortex-M4F, 1.27DMIPS/MHz, with single-precision float and SIMD (Single Instruction Multiple Data) for DSP. Support JTAG and SWD debug.

MCU includes 8-channel generic DMA and 8-channel audio DMA. Internal ROM is 850kB; internal SRAM is 830kB.

SIP in package, SPI NOR FLASH supports 4-wire random read and page program. Also with 8KB unified cache to improve random read performance.