Chapter 2: XPHY Architecture
Figure 2: Relationship Between a Single XPHY Nibble, XP IOL, and IOB
XP IOLXP IOLXP IOLXP IOLXP IOLXP IOLTX Tristate Control NIBBLESLICEXPHY NIBBLESLICE 5XPHY NIBBLESLICE 4XPHY NIBBLESLICE 3XPHY NIBBLESLICE 2XPHY NIBBLESLICE 1IOBIOBIOBIOBIOBIOBX21592-042319The following figure shows an XPHY NIBBLESLICE.
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XPHY NIBBLESLICE 0Chapter 2: XPHY Architecture
Figure 3: XPHY NIBBLESLICE with TX and RX Datapaths
Tristate Control Logic
Data fromProgrammable
Logic
8:1, 4:1, 2:1SerializationOutput DelayTXBidirectionalPin
Data to
Programmable
Logic
8-Deep FIFO1:8, 1:4, 1:2DeserializationInput DelayRXXPHY NIBBLESLICEIOBX21593-121219TX Datapath
The TX datapath is composed of the following:
?Serializer: The serializer supports 8:1, 4:1, and 2:1 serialization. This is set by theTX_DATA_WIDTH attribute.
?Output Delay: Output delays can delay outgoing serialized data up to 512 taps (0–511 taps),with a minimum of 625 ps of available delay.Refer to the Controlling Tristate Control section for latencies with and without the TX datapathusing tristate control.Related InformationControlling Delays
Controlling Tristate Control
RX Datapath
The RX datapath is composed of:
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Versal ACAP SelectIO Resources Architecture Manual
FPGA可编程逻辑器件芯片XC2V1000-5FGG256I中文规格书
