READ Operation
READ bursts are initiated with a READ command. The starting column and bank ad-dresses are provided with the READ command and auto precharge is either enabled ordisabled for that burst access. If auto precharge is enabled, the row being accessed isautomatically precharged at the completion of the burst. If auto precharge is disabled,the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address isavailable READ latency (RL) clocks later. RL is defined as the sum of posted CAS additivelatency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-ble in the mode register via the MRS command. Each subsequent data-out element isvalid nominally at the next positive or negative clock edge (that is, at the next crossingof CK and CK#). Figure 69 shows an example of RL based on a CL setting of 8 and an ALsetting of 0.
Figure 69: READ Latency
T0CK#CKCommandAddressREADBank a,Col nCL = 8, AL = 0DQS, DQS#DQDOnNOPNOPNOPNOPNOPNOPNOPT7T8T9T10T11T12T12Indicates breakin time scale
Transitioning DataDon’t Care
Notes:
1.DO n = data-out from column n.
2.Subsequent elements of data-out appear in the programmed order following DO n.
DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state onDQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The LOW stateon DQS and the HIGH state on DQS#, coincident with the last data-out element, is
known as the READ postamble (tRPST). Upon completion of a burst, assuming no othercommands have been initiated, the DQ goes High-Z. A detailed explanation of tDQSQ(valid data-out skew), tQH (data-out window hold), and the valid data window are de-picted in Figure 80 (page 171). A detailed explanation of tDQSCK (DQS transition skewto CK) is also depicted in Figure 80 (page 171).
Data from any READ burst may be concatenated with data from a subsequent READcommand to provide a continuous flow of data. The first data element from the newburst follows the last element of a completed burst. The new READ command should beissued tCCD cycles after the first READ command. This is shown for BL8 in Figure 70(page 165). If BC4 is enabled, tCCD must still be met, which will cause a gap in the dataoutput, as shown in Figure 71 (page 165). Nonconsecutive READ data is reflected in Figure 72 (page 166). DDR3 SDRAM does not allow interrupting or truncating anyREAD burst.
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4Gb_DDR3L.pdf - Rev. R 09/18 EN
4Gb: x4, x8, x16 DDR3L SDRAMPower-Down ModeFigure 100: Precharge Power-Down (Slow-Exit Mode) Entry and Exit
T0CK#CKtCKtCHtCLT1T2T3T4TaTa1TbCommandPRENOPNOPNOPNOPValid1Valid2tCPDEDtCKE (MIN)tXPtIStIHCKEtPDtIStXPDLLEnter power-down
modeExit power-down
mode
Indicates breakin time scale
Don’t Care
Notes:
1.Any valid command not requiring a locked DLL.2.Any valid command requiring a locked DLL.
Figure 101: Power-Down Entry After READ or READ with Auto Precharge (RDAP)
CK#CKREAD/RDAPT0T1Ta0Ta1Ta2Ta3Ta4Ta5Ta6Ta7Ta8Ta9Ta10Ta11Ta12CommandNOPNOPNOPNOPNOPNOPNOPNOPNOPtIStCPDEDNOPCKEAddressValidRL = AL + CLtPDDQS, DQS#DQ BL8DInDIDIn + 1n + 2DIn + 3DIn + 4DIn+ 5DIn + 6DIn + 7DQ BC4DInDIn + 1DIDIn + 2n + 3tRDPDENPower-down orself refresh entry
Indicates breakin time scale
Transitioning DataDon’t Care
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4Gb_DDR3L.pdf - Rev. R 09/18 EN
4Gb: x4, x8, x16 DDR3L SDRAMPower-Down ModeFigure 102: Power-Down Entry After WRITE
CK#CKWRITENOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPtIStCPDEDT0T1Ta0Ta1Ta2Ta3Ta4Ta5Ta6Ta7Tb0Tb1Tb2Tb3Tb4CommandNOPCKEAddressValidWL = AL + CWLtWRtPDDQS, DQS#DQ BL8DI nDIDIDIDIDIDIDI n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7DQ BC4DInDIn + 1DIn + 2DIn + 3tWRPDENPower-down orself refresh entry1
Indicates breakin time scale
Transitioning DataDon’t Care
Note:
1.CKE can go LOW 2tCK earlier if BC4MRS.
Figure 103: Power-Down Entry After WRITE with Auto Precharge (WRAP)
CK#CKWRAPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPNOPT0T1Ta0Ta1Ta2Ta3Ta4Ta5Ta6Ta7Tb0Tb1Tb2Tb3Tb4CommandtIStCPDEDCKEAddressValidA10WL = AL + CWLDQS, DQS#WR1tPDDQ BL8DInDIDIDIDIDIDIDI n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7DQ BC4DI nDIDIDI n + 1 n + 2 n + 3tWRAPDENStart internalprechargePower-down orself refresh entry2Indicates breakin time scale
Transitioning DataDon’t Care
Notes:
1.tWR is programmed through MR0[11:9] and represents tWRmin (ns)/tCK rounded up to
the next integer tCK.
2.CKE can go LOW 2tCK earlier if BC4MRS.
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4Gb_DDR3L.pdf - Rev. R 09/18 EN
4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
Figure 104: REFRESH to Power-Down Entry
T0
CK#CKtCKtCHtCLT1T2T3Ta0Ta1Ta2Tb0
CommandREFRESHNOPtCPDEDtISNOPNOPNOPValidtCKE (MIN)tPDCKEtREFPDENtXP (MIN)tRFC (MIN)1Indicates breakin time scale
Don’t Care
Note:
1.After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
Figure 105: ACTIVATE to Power-Down Entry
T0
CK#CKtCKtCHtCLT1T2T3T4T5T6T7
CommandACTIVENOPNOPAddressValidtCPDEDtIStPDCKEtACTPDENDon’t Care09005aef85af8fa8
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Power-Down Mode
Figure 108: Power-Down Exit to Refresh to Power-Down Entry
T0
CK#CKtCKtCHtCLT1T2T3T4Ta0Ta1Tb0
CommandNOPNOPNOPNOPREFRESHNOPNOPtCPDEDtXP1tIStIHtIStPDtXPDLL2CKEEnter power-downmodeExit power-downmodeEnter power-downmode09005aef85af8fa8
4Gb_DDR3L.pdf - Rev. R 09/18 EN
MEMORY存储芯片ADM3202ARUZ-REEL7中文规格书 - 图文
