找FPGA，上赛灵思半导体（深圳）有限公司
DS162 (v3.1.1) January 30, 2015
Product Specification
Spartan-6 FPGA Electrical Characteristics
Spartan?-6 LX and LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and AC electrical parameters of the Automotive XA Spartan-6 FPGAs and Defense-grade Spartan-6Q FPGAs devices are equivalent to the commercial specifications except where noted. The timing characteristics of the commercial (XC) -2 speed grade industrial device are the same as for a -2 speed grade commercial device. The -2Q and -3Q speed grades are
exclusively for the expanded (Q) temperature range. The timing characteristics are equivalent to those shown for the -2 and -3 speed grades for the Automotive and Defense-grade devices.
Spartan-6FPGA DC and AC characteristics are specified for commercial (C), industrial (I), and expanded (Q) temperature ranges. Only selected speed grades and/or devices might be available in the industrial or expanded temperature ranges for Automotive and Defense-grade devices. References to device names refer to all available variations of that part number (for example, LX75 could denote XC6SLX75, XA6SLX75, or XQ6SLX75). The Spartan-6 FPGA -3N speed grade designates devices that do not support MCB functionality.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Available device and package combinations can be found at:
DS162 (v3.1.1) January 30, 2015Product Specification
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 1:Absolute Maximum Ratings(1) (Cont’d)
Symbol
Description
DC
Commercial
20% overshoot duration8% overshoot duration(5)DC
All user and dedicated
Industrial
I/Os
20% overshoot duration4% overshoot duration(5)DC
Expanded (Q)20% overshoot duration
VIN and VTS(3)
I/O input voltage or voltage applied to 3-state output, relative to GND(4)
Commercial
4% overshoot duration(5)20% overshoot duration10% overshoot duration
Restricted to
maximum of 100 user IndustrialI/Os
20% overshoot duration10% overshoot duration8% overshoot duration(5)20% overshoot duration
Expanded (Q)10% overshoot duration
8% overshoot duration(5)
TSTG
Storage temperature (ambient)
Maximum soldering temperature(6)
(TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256)
TSOL
Maximum soldering temperature(6) (Pb-free packages: FGG484, FGG676, and FGG900)Maximum soldering temperature(6) (Pb packages: CS484, FT256, FG484, FG676, and FG900)
Tj
Notes:
1.2.3.4.5.6.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
When programming eFUSE, VFS≤VCCAUX. Requires up to 40mA current. For read mode, VFS can be between GND and 3.45V.
I/O absolute maximum limit applied to DC and AC signals. Overshoot duration is the percentage of a data period that the I/O is stressedbeyond 3.45V.
For I/O operation, refer to UG381: Spartan-6 FPGA SelectIO Resources User Guide.Maximum percent overshoot duration to meet 4.40V maximum.
TSOL is the maximum soldering temperature for component bodies. For soldering guidelines and thermal considerations,see UG385: Spartan-6 FPGA Packaging and Pinout Specification.
Units
–0.60 to 4.10–0.75 to 4.25–0.75 to 4.40–0.60 to 3.95–0.75 to 4.15–0.75 to 4.40–0.60 to 3.95–0.75 to 4.15–0.75 to 4.40–0.75 to 4.35–0.75 to 4.45–0.75 to 4.25–0.75 to 4.35–0.75 to 4.40–0.75 to 4.25–0.75 to 4.35–0.75 to 4.40–65to150+260+250+220+125
VVVVVVVVVVVVVVVVVV°C°C°C°C°C
15% overshoot duration(5)–0.75 to 4.40
Maximum junction temperature(6)
DS162 (v3.1.1) January 30, 2015Product Specification
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
eFUSE Read Endurance
Table11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For more information, see UG380: Spartan-6 FPGA Configuration User Guide.Table 11:eFUSE Read Endurance
SymbolDNA_CYCLESAES_CYCLES
Description
Number of DNA_PORT READ operations or JTAG ISC_DNA read command operations. Unaffected by SHIFT operations.
Number of JTAG FUSE_KEY or FUSE_CNTL read command operations. Unaffected by SHIFT operations.
Speed Grade-3
-3N
-2
-1L
Units(Min)Read CyclesRead Cycles
30,000,00030,000,000
DS162 (v3.1.1) January 30, 2015Product Specification
FPGA可编程逻辑器件芯片XC6SLX16-2CS中文规格书
