Introduction to the RocketIO GTX Transceiver
Overview
The RocketIO? GTX transceiver is a power-efficient transceiver for Virtex?-5 FPGAs. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications:???
Current Mode Logic (CML) serial drivers/buffers with configurable termination,voltage swing, and coupling.
Programmable TX pre-emphasis, RX equalization, and linear and decision feedbackequalization (DFE) for optimized signal integrity.
Line rates from 750Mb/s to 6.5Gb/s, with optional 5x digital oversampling requiredfor rates between 150Mb/s and 750Mb/s. The nominal operation range of the sharedPMA PLL is from 1.5GHz to 3.25GHz. These are nominal values, see DS202: Virtex-5FPGA Data Sheet for specifications.
Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channelbonding, and clock correction.
Fixed latency modes for minimized, deterministic datapath latency.
Beacon signaling for PCI Express? designs and Out-of-Band signaling includingCOM signal support for SATA designs.
RX/TX Gearbox provides header insertion and extraction support for 64B/66B and64B/67B (Interlaken) protocols.Receiver eye scan:
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Vertical eye scan in the voltage domain for testing purposesHorizontal eye scan in the time domain for testing purposes
The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref1], which discusses high-speed serial transceiver technology and its applications.
Table1-1 lists some of the standard protocols designers can implement using the GTX transceiver. The Xilinx? CORE Generator? tool includes a Wizard to automatically configure GTX transceivers to support one of these protocols or perform custom configuration (see Chapter2, “RocketIO GTX Transceiver Wizard”).
The GTX_DUAL tile offers a data rate range and features that allow physical layer support for various protocols as illustrated in Table1-1.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 1:Introduction to the RocketIO GTX Transceiver
Figure1-3 shows a diagram of a GTX_DUAL tile, containing two GTX transceivers and a shared resources block. The GTX_DUAL tile is the HDL primitive used to operate GTX transceivers in the FPGA.
X-Ref Target - Figure 1-3GTX_DUAL TilePackage PinsMGTTXP0MGTTXN0TXP0TXN0GTX TXTX-PMAGTX0FPGA PinsData From FPGA6TX-PCSTXDATA0[31:0]TXBYPASS8B10B0[3:0]TXCHARISK0[3:0]TXCHARDISPMODE0[3:0]TXCHARDISPVAL0[3:0]RXPOWERDOWN0[1:0]RXSTATUS0[2:0]RXDATA0[31:0]Data To FPGAMGTRXP0MGTRXN0RXP0RXN0GTX RX7RX-PMARX-PCSShared ResourcesRXDISPERR0[3:0]RXCHARISCOMMA0[3:0]RXCHARISSK0[3:0]RXRUNDISP0[3:0]RXVALID0[1:0]TXOUTCLK0TXUSRCLK0TXUSRCLK20RXUSRCLK0RXUSRCLK20RXRECCLK0CLKIN(1)DRPTXOUTCLK1TXUSRCLK1TXUSRCLK21RXUSRCLK1RXUSRCLK21RXRECCLK1MGTAVTTTXMGTAVTTRXMGTAVTTTXAVTTTXAVTTRXAVTTTX1SharedPMAPLLPLL LockDetection2ResetControlMGTAVCCMGTAVCCPLLMGTAVCCAVCCAVCCPLLAVCC3ClockingPowerControl45GTX1MGTTXP1MGTTXN1TXP1TXN1GTX TXTX-PMAData From FPGA6TXDATA1[31:0]TXBYPASS8B10B1[3:0]TXCHARISK1[3:0]TXCHARDISPMODE1[3:0]RXPOWERDOWN1[1:0]RXSTATUS1[2:0]RXDATA1[31:0]TX-PCSData To FPGAMGTRXP1MGTRXN1RXP1RXN1GTX RX7RX-PMARX-PCSRXDISPERR1[3:0]RXCHARISCOMMA1[3:0]RXCHARISSK1[3:0]RXVALID1[1:0]UG198_c1_02_010308Notes:
1.CLKIN is a simplification for a clock source. See Figure5-3, page97 for details on CLKIN.
Figure 1-3:GTX_DUAL Tile Block Diagram
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Ports and Attributes
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 1:Introduction to the RocketIO GTX Transceiver
Table 1-2:
Pin
GTX_DUAL Analog Pin Summary (Cont’d)
DirIn (Pad)In (Pad)
Description
Section (Page)
MGTRREF_RMGTRREF_LMGTRXN0MGTRXP0MGTRXN1MGTRXP1MGTTXN0MGTTXP0MGTTXN1MGTTXP1
TXT only: Reference resistor input for Analog Design the X1 column. Guidelines (page254)TXT only: Reference resistor input for Analog Design the X0 column. Guidelines (page254)
RX Termination and
Equalization (page162)
Differential complements forming a
In (Pad)differential receiver input pair for
each transceiver.
Out (Pad)
Differential complements forming a differential transmitter output pair for each transceiver.RX Termination and Equalization (page162)
Table1-3 lists alphabetically the signal names, clock domains, directions, and descriptions for the GTX_DUAL ports, and provides links to their detailed descriptions.
Table 1-3:
GTX_DUAL Port SummaryPort
CLKIN
DirIn
DomainAsync
Description
Reference clock input to the shared PMA PLL.DRP address bus.DRP interface clock.Enables DRP read or write operations.
Section (Page)Shared PMA PLL (page87), Clocking (page98),
Power Control (page110)Dynamic Reconfiguration Port (page117)
Dynamic Reconfiguration Port (page117)
Dynamic Reconfiguration Port (page117)
DADDR[6:0]DCLKDEN
DFECLKDLYADJ0[5:0]DFECLKDLYADJ1[5:0]
DFECLKDLYADJMONITOR0[5:0]DFECLKDLYADJMONITOR1[5:0]
InInInInOutOutOut
DCLKN/ADCLKRXUSRCLK2RXUSRCLK2RXUSRCLK2RXUSRCLK2
DFE clock delay adjust control for Decision Feedback each transceiver.Equalization (page167)DFE clock delay adjust monitor for each transceiver.
Decision Feedback Equalization (page167)Decision Feedback Equalization (page167)Decision Feedback Equalization (page167)Decision Feedback Equalization (page167)
DFEEYEDACMONITOR0[4:0]DFEEYEDACMONITOR1[4:0]DFESENSCAL0[2:0]DFESENSCAL1[2:0]DFETAP10[4:0]DFETAP11[4:0]
DFETAP1MONITOR0[4:0]DFETAP1MONITOR1[4:0]
Vertical Eye Scan for each transceiver (voltage domain).DFE calibration status.DFE tap 1 weight value control for each transceiver (5-bit resolution).
InRXUSRCLK2
OutRXUSRCLK2
DFE tap 1 weight value monitor
Decision Feedback
for each transceiver (5-bit
Equalization (page167)
resolution).
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 1:Introduction to the RocketIO GTX Transceiver
Table 1-3:GTX_DUAL Port Summary (Cont’d)Port
Dir
Domain
Description
Section (Page)
RXCHARISCOMMA0[3:0]RXCHARISCOMMA1[3:0]
OutRXUSRCLK2
Asserted when RXDATA is an 8B/10B comma.
RXCHARISCOMMA is
influenced by the setting of these
Configurable 8B/10B
attributes:
Decoder (page200)
DEC_MCOMMA_DETECT_0DEC_MCOMMA_DETECT_1DEC_PCOMMA_DETECT_0DEC_PCOMMA_DETECT_1Asserted when RXDATA is an 8B/10B K character.
FPGA channel bonding control. Used only by slaves.
Configurable 8B/10B Decoder (page200)Configurable Channel Bonding (Lane Deskew) (page219)
Configurable Channel Bonding (Lane Deskew) (page219)
Configurable Clock Correction (page212)Configurable Comma Alignment and Detection (page192)
Configurable Comma Alignment and Detection (page192)
FPGA RX Interface (page236)
RX Gearbox (page231)
RXCHARISK0[3:0]RXCHARISK1[3:0]RXCHBONDI0[3:0]RXCHBONDI1[3:0]RXCHBONDO0[3:0]RXCHBONDO1[3:0]RXCLKCORCNT0[2:0]RXCLKCORCNT1[2:0]RXCOMMADET0RXCOMMADET1RXCOMMADETUSE0RXCOMMADETUSE1RXDATA0[31:0]RXDATA1[31:0]RXDATAVALID0RXDATAVALID1RXDATAWIDTH0[1:0]RXDATAWIDTH1[1:0]RXDEC8B10BUSE0RXDEC8B10BUSE1RXDISPERR0[3:0]RXDISPERR1[3:0]RXELECIDLE0RXELECIDLE1RXENCHANSYNC0RXENCHANSYNC1
OutRXUSRCLK2
InRXUSRCLK
OutRXUSRCLKFPGA channel bonding control.Reports the status of the elastic buffer clock correction.Asserted when the comma alignment block detects a comma.
Activates the comma detection and alignment circuit.
Receive data bus of the receive interface to the FPGA.Data valid for RX Gearbox.
OutRXUSRCLK2
OutRXUSRCLK2
InRXUSRCLK2
OutOut
RXUSRCLK2RXUSRCLK2
InRXUSRCLK2
Selects the width of the RXDATA Configurable 8B/10B receive data connection to the Decoder (page200), FPGA FPGA.RX Interface (page236)Enables the 8B/10B decoder.Indicates if RXDATA was
received with a disparity error.
Configurable 8B/10B Decoder (page200)Configurable 8B/10B Decoder (page200)
InOut
RXUSRCLK2RXUSRCLK2
OutAsync
Indicates the differential voltage
RX OOB/Beacon Signaling
between RXN and RXP dropped
(page174)
below the minimum threshold.Enables channel bonding.
Configurable Channel Bonding (Lane Deskew) (page219)
InRXUSRCLK2
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
FPGA可编程逻辑器件芯片XCZU21DR-2FFVD1156I中文规格书 - 图文
