Advanced Features
clkena
If the system cannot tolerate the higher output frequencies when using pfdena higher value, the clkena signals can disable the output clocks until the PLL locks. The clkena signals control the regional, global, and external clock outputs. The clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. See Figure1–56 in the “Clock Control Block” section on page1–86 of this document for more information about the clkena signals.
Advanced Features
StratixII and Stratix II GX PLLs offer a variety of advanced features, such as counter cascading, clock switchover, PLL reconfiguration,
reconfigurable bandwidth, and spread-spectrum clocking. Table1–14 shows which advanced features are available in which type of StratixII or Stratix II GX PLL.
Table1–14.StratixII and Stratix II GX PLL Advanced Features
Advanced Feature
Counter cascadingClock switchoverPLL reconfigurationReconfigurable bandwidthSpread-spectrum clockingNote to Table1–14:(1)
StratixII and Stratix II GX fast PLLs only support manual clock switchover, not automatic clock switchover.
Availability
Enhanced PLLs
vvvvv
vvv
Fast PLLs(1)
Counter Cascading
The StratixII and Stratix II GX enhanced PLL supports counter cascading to create post-scale counters larger than 512. This is implemented by feeding the output of one counter into the input of the next counter in a cascade chain, as shown in Figure1–16.
Stratix II Device Handbook, Volume 2
PLLs in StratixII and StratixIIGX Devices
The switch-over state machine has two counters that count the edges of the primary and the secondary clocks; counter0 counts the number of inclk0 edges and counter1 counts the number of inclk1 edges. The counters get reset to zero when the count values reach 1, 1; 1, 2; 2, 1; or 2, 2 for inclock0 and inclock1, respectively. For example, if counter0 counts two edges, its count is set to two and if counter1 counts two edges before the counter0 sees another edge, they are both reset to 0. If for some reason one of the counters counts to three, it means the other clock missed an edge. The clkbad0 or clkbad1 signal goes high, and the switchover circuitry signals a switch condition. See Figure1–19.
Stratix II Device Handbook, Volume 2
Advanced Features
switchover circuit is edge-sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes high again, the process repeats.
clkswitch and automatic switch only work if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available.
Figure1–20.Clock Switchover Using the CLKSWITCH Control
inclk0Note(1)
inclk1muxoutclkswitchactiveclockclklossclk0badclk1badNote to Figure1–20:(1)
Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clockswitchover event. Failing to meet this requirement causes the clock switchover to not function properly.
Figure1–21 shows a simulation of using switchover for two different reference frequencies. In this example simulation, the reference clock is either 100 or 66 MHz. The PLL begins with fIN=100 MHz and is allowed to lock. At 20 ?s, the clock is switched to the secondary clock, which is at 66 MHz.
Stratix II Device Handbook, Volume 2
Reconfigurable Bandwidth
The charge pump current directly affects the PLL bandwidth. The higher the charge pump current, the higher the PLL bandwidth. You can choose from a fixed set of values for the charge pump current. Figure1–31 shows the loop filter and the components that can be set through the QuartusII software. The components are the loop filter resistor, R, and the high frequency capacitor, CH, and the charge pump current, IUPorIDN.Figure1–31.Loop Filter Programmable Components
IUPPFDRChIDNCSoftware Support
The QuartusII software provides two levels of bandwidth control. Megafunction-Based Bandwidth Setting
The first level of programmable bandwidth allows you to enter a value for the desired bandwidth directly into the QuartusII software using the altpll megafunction. You can also set the bandwidth parameter in the altpll megafunction to the desired bandwidth. The QuartusII software selects the best bandwidth parameters available to match your
bandwidth request. If the individual bandwidth setting request is not available, the QuartusII software selects the closest achievable value.Advanced Bandwidth Setting
An advanced level of control is also possible using advanced loop filter parameters. You can dynamically change the charge pump current, loop filter resistor value, and the loop filter (high frequency) capacitor value.
Stratix II Device Handbook, Volume 2
PLLs in StratixII and StratixIIGX Devices
Software Support
You can enter the desired down-spread percentage and modulation
frequency in the altpll megafunction through the QuartusII software. Alternatively, the downspread parameter in the altpll megafunction can be set to the desired down-spread percentage. Timing analysis
ensures the design operates at the maximum spread frequency and meets all timing requirements.
f
For more information about PLL software support in the QuartusII software, see the altpll Megafunction User Guide.
Guidelines
If the design cascades PLLs, the source (upstream) PLL should have a low-bandwidth setting, while the destination (downstream) PLL should have a high-bandwidth setting. The upstream PLL must have a
low-bandwidth setting because a PLL does not generate jitter higher than its bandwidth. The downstream PLL must have a high bandwidth setting to track the jitter. The design must use the spread-spectrum feature in a low-bandwidth PLL, and, therefore, the QuartusII software automatically sets the spread-spectrum PLL bandwidth to low.1
If the programmable or reconfigurable bandwidth features are used, then you cannot use spread spectrum.
StratixII and Stratix II GX devices can accept a spread-spectrum input with typical modulation frequencies. However, the device cannot
automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of the downstream PLL.
Spread spectrum can have a minor effect on the output clock by
increasing the period jitter. Period jitter is the deviation of a clock’s cycle time from its previous cycle position. Period jitter measures the variation of the clock output transition from its ideal position over consecutive edges.
With down-spread modulation, the peak of the modulated waveform is the actual target frequency. Therefore, the system never exceeds the maximum clock speed. To maintain reliable communication, the entire system and subsystem should use the StratixII and Stratix II GX device as the clock source. Communication could fail if the StratixII or
StratixIIGX logic array is clocked by the spread-spectrum clock, but the data it receives from another device is not clocked by the spread spectrum.
Stratix II Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S30B956C5N中文规格书 - 图文
