Figure2–55.Output TIming Diagram in DDR Mode
CLKA1A2A3A4From InternalRegistersB1B2B3B4DDR outputB1A1B2A2B3A3B4A4The StratixII IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock. This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, StratixII devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces. StratixII devices support DDR and DDR2 SDRAM, QDR II SRAM, RLDRAMII, and SDR SDRAM memory interfaces. In every StratixII device, the I/O banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table2–14 shows the number of DQ and DQS buses that are supported per device.
Table2–14.DQS & DQ Bus Mode Support(Part 1 of2)Device
EP2S15EP2S30EP2S60
Note(1)Number of ×8/×9 Groups
48484818
Package
484-pin FineLine BGA672-pin FineLine BGA484-pin FineLine BGA672-pin FineLine BGA484-pin FineLine BGA672-pin FineLine BGA1,020-pin FineLine BGA
Number of ×4Groups
81881881836
Number of Number of ×16/×18 Groups×32/×36 Groups
0404048
0000004
Stratix II Device Handbook, Volume 1
I/O Structure
Table2–14.DQS & DQ Bus Mode Support(Part 2 of2)Device
EP2S90
Note(1)Number of ×8/×9 Groups
481818818181818
Package
484-pin Hybrid FineLine BGA 780-pin FineLine BGA1,020-pin FineLine BGA1,508-pin FineLine BGA
Number of ×4Groups
81836361836363636
Number of Number of ×16/×18 Groups×32/×36 Groups
048848888
004404444
EP2S130780-pin FineLine BGA
1,020-pin FineLine BGA1,508-pin FineLine BGA
EP2S1801,020-pin FineLine BGA
1,508-pin FineLine BGA
Notes to Table2–14:(1)
Check the pin table for each DQS/DQ group in the different modes.
A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal.
The StratixII device has two phase-shifting reference circuits, one on the top and one on the bottom of the device. The circuit on the top controls the compensated delay elements for all DQS pins on the top. The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. In addition, PLL clock outputs can also feed the phase-shifting reference circuits.
Figure2–56 illustrates the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device.
Stratix II Device Handbook, Volume 1
StratixII Architecture
The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when the I/O pin has been configured for differential signals.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 kΩ to weakly pull the signal level to the last-driven state. See the DC & Switching Characteristics chapter in the StratixII Device Handbook, Volume 1, for the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level. This information is provided for each VCCIO voltage level.
The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration.
Programmable Pull-Up Resistor
Each StratixII device I/O pin provides an optional programmable
pull-up resistor during user mode. If you enable this feature for an I/O pin, the pull-up resistor (typically 25 kΩ) weakly holds the output to the VCCIO level of the output pin’s bank.
Programmable pull-up resistors are only supported on user I/O pins, and are not supported on dedicated configuration pins, JTAG pins or dedicated clock pins.
Advanced I/O Standard Support
StratixII device IOEs support the following I/O standards:
■■■■■■■■■■■■■
3.3-V LVTTL/LVCMOS2.5-V LVTTL/LVCMOS1.8-V LVTTL/LVCMOS1.5-V LVCMOS3.3-V PCI
3.3-V PCI-X mode 1LVDS
LVPECL (on input and output clocks only)HyperTransport technology
Differential 1.5-V HSTL Class I and IIDifferential 1.8-V HSTL Class I and IIDifferential SSTL-18 Class I and IIDifferential SSTL-2 Class I and II
Stratix II Device Handbook, Volume 1
I/O Structure
■■■■■1.5-V HSTL Class I and II1.8-V HSTL Class I and II1.2-V HSTL
SSTL-2 Class I and IISSTL-18 Class I and II
Table2–16 describes the I/O standards supported by StratixII devices.
Table2–16.StratixII Supported I/O Standards (Part 1 of2)
I/O Standard
LVTTLLVCMOS2.5 V1.8 V
1.5-V LVCMOS3.3-V PCI
3.3-V PCI-X mode 1LVDSLVPECL (1)
Differential 1.5-V HSTL Class I and II (2)Differential 1.8-V HSTL Class I and II (2)
Type
Single-endedSingle-endedSingle-endedSingle-endedSingle-endedSingle-endedSingle-endedDifferentialDifferentialDifferentialDifferential
Input Reference Output Supply Board Termination Voltage (VREF) (V)Voltage (VCCIO) (V)Voltage (VTT) (V)
----------0.750.900.901.250.60.750.90.90
3.33.32.51.81.53.33.32.5 (3)3.32.51.51.81.82.51.21.51.81.8
----------0.750.900.901.250.60.750.90.90
HyperTransport technologyDifferential
Differential SSTL-18 Class DifferentialI and II (2)
Differential SSTL-2 ClassI Differentialand II (2)1.2-V HSTL(4)
1.5-V HSTL Class I and II1.8-V HSTL Class I and IISSTL-18 Class I and II
Voltage-referencedVoltage-referencedVoltage-referencedVoltage-referenced
Stratix II Device Handbook, Volume 1
StratixII Architecture
Table2–16.StratixII Supported I/O Standards (Part 2 of2)
I/O Standard
SSTL-2 Class I and IINotes to Table2–16:(1)(2)(3)
This I/O standard is only available on input and output column clock pins.
This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clockpins in I/O banks 9,10, 11, and 12.
VCCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 9, 10, 11, and 12). The clock input pins supporting LVDS on banks 3, 4, 7, and 8 use VCCINT for LVDS input operations and have no dependency on the VCCIO level of the bank.
1.2-V HSTL is only supported in I/O banks 4,7, and 8.
Type
Voltage-referenced
Input Reference Output Supply Board Termination Voltage (VREF) (V)Voltage (VCCIO) (V)Voltage (VTT) (V)
1.25
2.5
1.25
(4)
Stratix II Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S25B672C7N中文规格书 - 图文
