Chapter2
Configuration Interface Basics
This chapter provides quick access to the most commonly used configuration solutions for Spartan?-6 FPGA devices. It includes several different methods and gives the appropriate connections, terminations, signal definitions, and basic timing descriptions. Additional detail is included in Chapter9, Advanced Configuration Interfaces, which covers more advanced arrangements as well as more detail on error recovery and further explanation of some of the ideas initially summarized here.
Spartan-6 devices support all the configuration modes supported by the Extended
Spartan-3A family. However, the difference is Spartan-6 devices only expose two mode pins M[1:0], which define the configuration modes, instead of three mode pins M[2:0] used by the ExtendedSpartan-3Afamily. The mode pins are described in Table2-1. Detailed interface timing information is located in DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics.
Table 2-1:Spartan-6 FPGA Configuration Modes
Configuration Mode
Master Serial/SPIMaster SelectMAP/BPI(2)JTAG(3)
Slave SelectMAP(2)Slave Serial(4)
Notes:
1.Utilizing dual and quad SPI modes.
2.Parallel configuration mode bus is auto-detected by the configuration logic.
3.Spartan-6 devices also have a dedicated four-wire JTAG (IEEE Std 1149.1) port that is always available to the FPGA regardless of the mode pin settings.
4.Default setting due to internal pull-up termination on Mode pins.
M[1:0]
0100xx1011
Bus Width
1, 2, 4(1)8, 1618, 161
CCLK Direction
OutputOutputInput (TCK)InputInput
JTAG Interface
While there is no specific mode for JTAG, the JTAG interface is available as a configuration interface any time the device is powered. For more information, refer to Chapter3, Boundary-Scan and JTAG Configuration.
Serial Configuration Interface
In serial configuration modes, the FPGA is configured by loading one configuration bit per CCLK cycle:
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
SelectMAP Configuration Interface
Table2-3 describes the SelectMAP configuration interface.
Table 2-3:Spartan-6 FPGA SelectMAP Configuration Interface PinsPin Name
M[1:0]CCLK
Type
InputInput and Output3-StateBidirectionalBidirectional, Open-Drain or ActiveInput or Output, Open-Drain
Dedicated or Dual-Purpose
Dual-PurposeDual-PurposeDual-PurposeDedicated
Description
Mode pins - determine configuration mode.See Table2-1, page23.
Configuration clock source for all configuration modes except JTAG. See Board Layout for Configuration Clock (CCLK), page56.
Configuration and readback data bus, clocked on the rising edge of CCLK. See Parallel Bus Bit Order, page81.
Active-High signal indicating configuration is complete:
0 = FPGA not configured1 = FPGA configured Before the Mode pins are sampled, INIT_B is an input that can be held Low to delay configuration. After the Mode pins are sampled, INIT_B is an open-drain, active-Low output indicating whether a CRC error occurred during configuration:0 = CRC error1 = No CRC error
When the SEU detection function is enabled,
INIT_B is reserved and cannot be used as user I/O.Active-Low asynchronous full-chip reset.Active-Low chip select to enable the SelectMAP data bus (see SelectMAP Data Loading, page35):0 = SelectMAP data bus enabled1 = SelectMAP data bus disabledDetermines the direction of the D[x:0] data bus (see SelectMAP Data Loading, page35): 0 = inputs1 = outputs
RDWR_B input can only be changed while CSI_B is deasserted, otherwise an ABORT occurs (see SelectMAP ABORT, page157). RDWR_B can be used as a VREF pin, but doing so prevents use of the SelectMAP configuration mode.
Parallel daisy-chain active-Low chip select output. Not used in single FPGA applications.
This output pin is used during readback. This pin can toggle during configuration.
D[15:0]
DONE
INIT_B
Dual-Purpose
PROGRAM_BCSI_B
InputInput
DedicatedDual-Purpose
RDWR_BInput
Dual-Purpose
CSO_BBUSY
OutputOutput
Dual-PurposeDual-Purpose
Single Device SelectMAP Configuration
This section describes how to configure a single device in SelectMAP mode, where the FPGA connects either to a Platform Flash PROM or to a microprocessor or CPLD.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
SPI Configuration Interface
Master SPI Dual (x2) and Quad (x4) Read Commands
The Master SPI configuration mode in Spartan-6 FPGAs supports the SPI flash memory dual (x2) and quad bit (x4) memory fast output read commands. To enable this
configuration method in software, the BitGen spi_buswidth option is used to create a .bit file for SPI x2 or x4. The FPGA still initially boots in x1 mode and then switches to x2 or x4 mode.
In x2 mode, the Fast-Read Dual Output (3Bh) instruction is issued and is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DO and DIO (MOSI), instead of just DO. This allows data to be transferred from the dual output at twice the rate of standard SPI devices. The timing diagram of the Master Serial SPI configuration mode using an SPI flash with dual read-bit command (3Bh) is shown in Figure2-17.
X-Ref Target - Figure 2-17CSO_BCCLKMOSI/MISO[0]DIN/MISO[1]Read Command24-Bit AddressDummyByte (8 Bits)D6D4D2D0D7D5D3D1Data Byte 1UG380_c2_17_052009Figure 2-17:Timing Diagram of SPI Dual-Read Bit Command (3Bh)
In x4 mode, the Fast-Read Quad Output (6Bh) instruction is issued and is similar to the standard Fast Read (0Bh) instruction except that data is output on four data pins, instead of just DO. This allows data to be transferred from the quad output at four times the rate of standard SPI devices. The timing diagram of the Master Serial SPI configuration mode using an SPI flash with quad read bit command (6Bh) is shown in Figure2-18.
X-Ref Target - Figure 2-18CSO_BCCLKMOSI/MISO[0]DIN/MISO[1]MISO[2]MISO[3]D0–D7 Next D0–D7 Read Command24-Bit AddressDummyByte (8 Bits)D4D0D4D0D5D1D5D1D6D2D6D2D7D3D7D3Data Byte 1 This corresponds with the first two columns of data.Data Byte 2 This corresponds with the last two columns of data.UG380_c2_18_052009Figure 2-18:Timing Diagram of SPI Quad-Read Bit Command (6Bh)
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
POST_CRC_INTERNAL
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Chapter 4:User Primitives
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2024
FPGA可编程逻辑器件芯片XC2S150-5FG256C中文规格书 - 图文
